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| mc68hc 1 1ed0ts/d rev 1 mc68hc11ed0 t echnical summary hcmos microcontroller unit m 6 8h c 11m 6 11m68hc11 m 8 hc11m68hc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
blank f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc11ed0 ? rev. 1.0 te c h n i c a l s u m m a r y mc68hc11ed0 technical summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical summary mc68hc11ed0 ? rev. 1.0 technical summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc11ed0 ? rev. 1.0 te c h n i c a l s u m m a r y list of sections technical summary ? mc68hc11ed0 list of sections section 1. general description . . . . . . . . . . . . . . . . . . . . 15 section 2. pin assignments . . . . . . . . . . . . . . . . . . . . . . . 19 section 3. central processor unit (cpu) . . . . . . . . . . . . 23 section 4. operating modes and on-chip memory . . . . 43 section 5. resets and interrupts . . . . . . . . . . . . . . . . . . . 57 section 6. parallel input/output (i/o) ports . . . . . . . . . . 65 section 7. serial communications interface (sci) . . . . . 71 section 8. serial peripheral interface (spi). . . . . . . . . . . 81 section 9. timing system. . . . . . . . . . . . . . . . . . . . . . . . . 87 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical summary mc68hc11ed0 ? rev. 1.0 list of sections list of sections f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc11ed0 ? rev. 1.0 te c h n i c a l s u m m a r y table of contents technical summary ? mc68hc11ed0 table of contents section 1. general description 1.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.4 structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.5 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 section 2. pin assignments 2.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3 44-pin plastic-leaded chip carrier (plcc) . . . . . . . . . . . . . . .20 2.4 44-pin quad flat pack (qfp). . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.5 40-pin plastic dual in-line package (dip) . . . . . . . . . . . . . . . . 22 section 3. central processor unit (cpu) 3.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.3.1 accumulators a, b, and d . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.3.2 index register x (ix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.3.3 index register y (iy) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.3.4 stack pointer (sp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.3.5 program counter (pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical summary mc68hc11ed0 ? rev. 1.0 table of contents table of contents 3.3.6 condition code register (ccr) . . . . . . . . . . . . . . . . . . . . . . 29 3.3.6.1 carry/borrow (c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.3.6.2 overflow (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.3.6.3 zero (z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 3.3.6.4 negative (n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.3.6.5 i-interrupt mask (i) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.3.6.6 half carry (h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 3.3.6.7 x-interrupt mask (x). . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 3.3.6.8 stop disable (s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.4 data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.5 opcodes and operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.6 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.6.1 immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.6.2 direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.6.3 extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.6.4 indexed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.6.5 inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.6.6 relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.7 instruction set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 section 4. operating modes and on-chip memory 4.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.3 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.3.1 bootstrap mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.3.2 special test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.3.3 expanded operating mode . . . . . . . . . . . . . . . . . . . . . . . . .45 4.4 mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.5 on-chip memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.5.1 memory map and register block . . . . . . . . . . . . . . . . . . . . .49 4.5.2 ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mc68hc11ed0 ? rev. 1.0 technical summary table of contents section 5. resets and interrupts 5.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.3 resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.4 system configuration options register . . . . . . . . . . . . . . . . . . 60 5.5 arm/reset cop timer circuitry register . . . . . . . . . . . . . . . . . 61 5.6 configuration control register . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.7 highest priority i-bit interrupt and miscellaneous register . . .63 section 6. parallel input/output (i/o) ports 6.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.3 port a data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.4 pulse accumulator control register. . . . . . . . . . . . . . . . . . . . . 67 6.5 port d data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.6 port d data direction register . . . . . . . . . . . . . . . . . . . . . . . . . 69 section 7. serial communications interface (sci) 7.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 7.3 sci registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 7.3.1 baud rate register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.3.2 serial communications control register 1 . . . . . . . . . . . . . 77 7.3.3 serial communications control register 2 . . . . . . . . . . . . . 78 7.3.4 serial communication status register. . . . . . . . . . . . . . . . . 79 7.3.5 serial communications data register . . . . . . . . . . . . . . . . . 80 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical summary mc68hc11ed0 ? rev. 1.0 table of contents table of contents section 8. serial peripheral interface (spi) 8.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 8.3 spi registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 8.3.1 serial peripheral control register . . . . . . . . . . . . . . . . . . .83 8.3.2 serial peripheral status register . . . . . . . . . . . . . . . . . . . .85 8.3.3 serial peripheral data i/o register . . . . . . . . . . . . . . . . . . .86 section 9. timing system 9.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 9.3 timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 9.3.1 timer compare force register . . . . . . . . . . . . . . . . . . . . . . 91 9.3.2 output compare 1 mask register . . . . . . . . . . . . . . . . . . . . 92 9.3.3 output compare 1 data register. . . . . . . . . . . . . . . . . . . . . 92 9.3.4 timer count register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 9.3.5 timer input capture registers . . . . . . . . . . . . . . . . . . . . . . .94 9.3.6 timer output compare registers . . . . . . . . . . . . . . . . . . . . 95 9.3.7 timer input capture 4/output compare 5 register . . . . . . .96 9.3.8 timer control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 9.3.9 timer control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 9.3.10 timer interrupt mask 1 register. . . . . . . . . . . . . . . . . . . . . . 99 9.3.11 timer interrupt flag 1 register . . . . . . . . . . . . . . . . . . . . .100 9.3.12 timer interrupt mask 2 register. . . . . . . . . . . . . . . . . . . . .100 9.3.13 timer interrupt flag register 2 . . . . . . . . . . . . . . . . . . . . .102 9.4 pulse accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 9.4.1 pulse accumulator control register . . . . . . . . . . . . . . . . . 104 9.4.2 pulse accumulator counter register . . . . . . . . . . . . . . . . .106 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc11ed0 ? rev. 1.0 te c h n i c a l s u m m a r y list of figures technical summary ? mc68hc11ed0 list of figures figure title page 1-1 mc68hc11ed0 block diagram . . . . . . . . . . . . . . . . . . . . . . . .17 2-1 pin assignments for 44-pin plcc . . . . . . . . . . . . . . . . . . . . . . 20 2-2 pin assignments for 44-pin qfp . . . . . . . . . . . . . . . . . . . . . . . 21 2-3 pin assignments for 40-pin dip . . . . . . . . . . . . . . . . . . . . . . . .22 3-1 programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 3-2 stacking operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4-1 address and data demultiplexing . . . . . . . . . . . . . . . . . . . . . . 46 4-2 highest priority i-bit interrupt and miscellaneous register (hprio) . . . . . . . . . . . . . . . . .47 4-3 mc68hc11ed0 memory map . . . . . . . . . . . . . . . . . . . . . . . . . 49 4-4 register and control bit assignments . . . . . . . . . . . . . . . . . . .50 4-5 ram and register mapping register (init) . . . . . . . . . . . . . . .56 5-1 system configuration options register (option) . . . . . . . . . 60 5-2 arm/reset cop timer circuitry register (coprst). . . . . . . . 61 5-3 system configuration register (config) . . . . . . . . . . . . . . . . 62 5-4 highest priority i-bit interrupt and miscellaneous register (hprio) . . . . . . . . . . . . . . . . .63 6-1 port a data register (porta) . . . . . . . . . . . . . . . . . . . . . . . . . 66 6-2 pulse accumulator control register (pactl) . . . . . . . . . . . . . 67 6-3 port d data register (portd). . . . . . . . . . . . . . . . . . . . . . . . . 68 6-4 port d data direction register (ddrd) . . . . . . . . . . . . . . . . . . 69 7-1 sci transmitter block diagram . . . . . . . . . . . . . . . . . . . . . . . .72 7-2 sci receiver block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 73 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical summary mc68hc11ed0 ? rev. 1.0 list of figures list of figures figure title page 7-3 baud rate register (baud) . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7-4 sci baud rate generator clock diagram . . . . . . . . . . . . . . . .76 7-5 serial communications control register 1 (sccr1) . . . . . . . . 77 7-6 serial communications control register 2 (sccr2) . . . . . . . . 78 7-7 serial communications status register (scsr) . . . . . . . . . . . 79 7-8 serial communications data register (scdr) . . . . . . . . . . . . 80 8-1 spi block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 8-2 serial peripheral control register (spcr). . . . . . . . . . . . . . . .83 8-3 spi transfer format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 8-4 serial peripheral status register (spsr) . . . . . . . . . . . . . . . .85 8-5 serial peripheral data i/o register (spdr) . . . . . . . . . . . . . . .86 9-1 timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 9-2 timer compare force register (cforc) . . . . . . . . . . . . . . . . 91 9-3 output compare 1 mask register (oc1m) . . . . . . . . . . . . . . . 92 9-4 output compare 1 data register (oc1d) . . . . . . . . . . . . . . . . 92 9-5 timer count register (tcnt). . . . . . . . . . . . . . . . . . . . . . . . . . 93 9-6 timer input capture register 1 (tic1) . . . . . . . . . . . . . . . . . . .94 9-7 timer input capture register 2 (tic2) . . . . . . . . . . . . . . . . . . .94 9-8 timer input capture register 3 (tic3) . . . . . . . . . . . . . . . . . . .94 9-9 timer output compare register 1 (toc1). . . . . . . . . . . . . . . .95 9-10 timer output compare register 2 (toc2). . . . . . . . . . . . . . . .95 9-11 timer output compare register 3 (toc3). . . . . . . . . . . . . . . .95 9-12 timer output compare register 4 (toc4). . . . . . . . . . . . . . . .96 9-13 timer input capture4/output compare 5 register (ti4/o5) . .96 9-14 timer control register 1 (tctl1) . . . . . . . . . . . . . . . . . . . . . . 97 9-15 timer control register 2 (tctl2) . . . . . . . . . . . . . . . . . . . . . . 98 9-16 timer interrupt mask 1 register (tmsk1) . . . . . . . . . . . . . . . .99 9-17 timer interrupt flag 1 register (tflg1) . . . . . . . . . . . . . . . .100 9-18 timer interrupt mask 2 register (tmsk2) . . . . . . . . . . . . . . .100 9-19 timer interrupt flag 2 register (tflg2) . . . . . . . . . . . . . . . .102 9-20 pulse accumulator system block diagram . . . . . . . . . . . . . . 103 9-21 pulse accumulator control register (pactl) . . . . . . . . . . . . 104 9-22 pulse accumulator counter register (pacnt) . . . . . . . . . . .106 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc11ed0 ? rev. 1.0 te c h n i c a l s u m m a r y list of tables technical summary ? mc68hc11ed0 list of tables table title page 1-1 device ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3-1 reset vector comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 3-2 instruction set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 5-1 interrupt and reset vector assignments . . . . . . . . . . . . . . . . . 59 5-2 cop timer rate select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5-3 highest priority interrupt selection . . . . . . . . . . . . . . . . . . . . . . 64 6-1 input/output ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 7-1 prescaler rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7-2 baud rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 8-1 spi clock rate selects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 9-1 timer summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 9-2 timer output compare actions . . . . . . . . . . . . . . . . . . . . . . . .97 9-3 timer control configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 9-4 timer prescale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 9-5 pulse accumulator timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 9-6 rti rates (period length) . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 9-7 rti rates (frequency) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical summary mc68hc11ed0 ? rev. 1.0 list of tables list of tables f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc11ed0 ? rev. 1.0 te c h n i c a l s u m m a r y general description technical summary ? mc68hc11ed0 section 1. general description 1.1 contents 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.4 structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.5 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.2 introduction the mc68hc11ed0 is a low-cost member of the m68hc11 family of microcontrollers (mcu). this mcu has a multiplexed address/data bus and is characterized by high speed and low-power consumption. the fully static design allows operation at frequencies from 3 mhz to dc. pin count is minimized for cost-sensitive applications. because there is no on-chip read-only memory (rom), this device is optimized for expanded-bus systems. on-chip serial peripheral interface (spi) and serial communications interface (sci) provide a convenient means or transferring data to and from internal random-access memory (ram). refer to figure 1-1 . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical summary mc68hc11ed0 ? rev. 1.0 general description general description 1.3 features features include: m68hc11 cpu power-saving stop and wait modes 512 bytes of ram multiplexed address and data buses enhanced 16-bit timer with 4-stage programmable prescaler ? three input capture (ic) channels ? four output compare (oc) channels ? one additional channel, selectable as fourth ic or fifth oc 8-bit pulse accumulator real-time interrupt circuit computer operating properly (cop) watchdog clock monitor enhanced asynchronous non-return-to-zero (nrz) sci enhanced spi eight bidirectional input/output (i/o) lines three input-only lines three output-only lines (one output-only line in 40-pin package) packaging options: ? 44-pin plastic-leaded chip carrier (plcc) ? 44-pin quad flat pack (qfp) ? 40-pin plastic dual in-line package (dip) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description structure mc68hc11ed0 ? rev. 1.0 technical summary general description 1.4 structure see figure 1-1 for a block diagram of the mc68hc11ed0 mcu. figure 1-1. mc68hc11ed0 block diagram addr7/data7 addr6/data6 addr5/data5 addr4/data4 addr3/data3 addr2/data2 addr1/data1 addr0/data0 mode control osc clock logic interrupt logic 256 bytes bootstrap rom serial peripheral interface spi serial communication interface sci m68hc11 cpu control port d txd rxd ss sck mosi miso pd5/ss pd0/rxd as r/w low-order address/data r/w as addr15 port a pa7/pai/ioc1 timer system cop timer pulse accumulator oc2 oc3 oc4 oc5/ic4/oc1 ic1 ic2 ic3 pai periodic interrupt moda/ lir modb/ v stby xtal extal e irq xirq reset pd4/sck pd3/mosi pd2/miso pd1/txd pa6/oc2/oc1 (1) pa5/oc3/oc1 pa4/oc4/oc1 (1) pa3/ic4/oc5/oc1 pa2/ic1 pa1/ic2 pa0/ic3 addr14 addr13 addr12 addr11 addr10 addr9 addr8 v dd v ss note 1. not bonded in 40-pin package 512 bytes ram high-order address f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical summary mc68hc11ed0 ? rev. 1.0 general description general description 1.5 ordering information table 1-1 provides ordering information for the mc68hc11ed0. refer to section 2. pin assignments . table 1-1. device ordering information package temperature description frequency mc order number 44-pin plcc ? 40 c to +85 c no rom/eprom no eeprom 512 bytes ram 2 mhz MC68HC11ED0CFN2 3 mhz mc68hc11ed0cfn3 ? 40 c to +105 c 2 mhz mc68hc11ed0vfn2 3 mhz mc68hc11ed0vfn3 ? 40 c to +125 c 2 mhz mc68hc11ed0mfn2 3 mhz mc68hc11ed0mfn3 44-pin qfp ? 40 c to +85 c no rom/eprom no eeprom 512 bytes ram 2 mhz mc68hc11ed0cfu2 3 mhz mc68hc11ed0cfu3 ? 40 c to +105 c 2 mhz mc68hc11ed0vfu2 3 mhz mc68hc11ed0vfu3 ? 40 c to +125 c 2 mhz mc68hc11ed0mfu2 3 mhz mc68hc11ed0mfu3 44-pin dip ? 40 c to +85 c no rom/eprom no eeprom 512 bytes ram 2 mhz mc68hc11ed0cp2 3 mhz mc68hc11ed0cp3 ? 40 c to +105 c 2 mhz mc68hc11ed0vp2 3 mhz mc68hc11ed0vp3 ? 40 c to +125 c 2 mhz mc68hc11ed0mp2 3 mhz mc68hc11ed0mp3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc11ed0 ? rev. 1.0 te c h n i c a l s u m m a r y pin assignments technical data ? mc68hc11ed0 section 2. pin assignments 2.1 contents 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3 44-pin plastic-leaded chip carrier (plcc) . . . . . . . . . . . . . . .20 2.4 44-pin quad flat pack (qfp). . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.5 40-pin plastic dual in-line package (dip) . . . . . . . . . . . . . . . . 22 2.2 introduction the mc68hc11ed0 pin assignments are shown here for these packages: 44-pin plastic-leaded chip carrier (plcc) 44-pin quad flat pack (qfp) 40-pin plastic dual in-line package (dip) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical summary mc68hc11ed0 ? rev. 1.0 pin assignments pin assignments 2.3 44-pin plastic-leaded chip carrier (plcc) refer to figure 2-1 for the 44-pin plcc pin assignments. figure 2-1. pin assignments for 44-pin plcc addr6/data6 addr1/data1 addr10 addr5/data5 addr4/data4 addr7/data7 xirq r/w as reset irq pd0/rxd pd1/txd addr8 addr9 addr11 addr12 addr13 addr14 addr15 nc pa0/ic3 pa1/ic2 addr0/data0 v ss ev ss (1) xtal extal e moda/lir modb/v stby addr3/data3 addr2/data2 pd2/miso pd3/mosi pd4/sck pd5/ss v dd pa7/pai/oc1 pa6/oc2/oc1 (1) pa5/oc3/oc1 pa4/oc4/oc1 (1) pa3/ic4/oc5/oc1 pa2/ic1 7 8 9 10 11 12 13 14 15 16 17 18 19 20 24 21 22 23 25 26 27 28 39 38 37 36 35 34 33 32 31 30 29 note 1. not bonded in 40-pin package 6 5 4 3 2 1 44 43 42 41 40 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . pin assignments 44-pin quad flat pack (qfp) mc68hc11ed0 ? rev. 1.0 technical summary pin assignments 2.4 44-pin quad flat pack (qfp) refer to figure 2-2 for the 44-pin qfp pin assignments. figure 2-2. pin assignments for 44-pin qfp note 1. not bonded in 40-pin package pa3/ic4/oc5/oc1 reset addr10 as r/w xirq addr7/data7 addr6/data6 addr5/data5 addr4/data4 irq pd0/rxd pd1/txd addr8 addr9 addr11 addr12 addr13 addr14 addr15 nc pa0/ic3 pa1/ic2 pd2/miso pd3/mosi pd4/sck pd5/ss v dd pa7/pai/oc1 pa6/oc2/oc1 (1) pa5/oc3/oc1 pa4/oc4/oc1 (1) pa2/ic1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 33 32 31 30 29 28 27 26 25 24 23 44 43 42 41 40 39 38 37 36 35 34 1 addr1/data1 addr3/data3 addr2/data2 addr0/data0 v ss ev ss (1) xtal extal e moda/lir modb/v stby f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical summary mc68hc11ed0 ? rev. 1.0 pin assignments pin assignments 2.5 40-pin plastic dual in-line package (dip) refer to figure 2-3 for the 40-pin dip pin assignments. figure 2-3. pin assignments for 40-pin dip v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 addr0/data0 addr1/data1 addr2/data2 addr3/data3 addr4/data4 addr5/data5 addr6/data6 addr7/data7 xirq r/w as reset irq pd0/rxd pd1/txd pd2/miso pd3/mosi pd4/sck pd5/ss v dd pa7/oc1 pa5/oc3/oc1 pa3/ic4/oc5/oc1 pa2/ic1 pa1/ic2 pa0/ic3 addr15 addr14 addr13 addr12 addr11 addr10 addr9 addr8 modb/v stby moda/lir e extal xtal f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc11ed0 ? rev. 1.0 te c h n i c a l s u m m a r y central processor unit (cpu) technical data ? mc68hc11ed0 section 3. central processor unit (cpu) 3.1 contents 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.3.1 accumulators a, b, and d . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.3.2 index register x (ix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.3.3 index register y (iy) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.3.4 stack pointer (sp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.3.5 program counter (pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 3.3.6 condition code register (ccr) . . . . . . . . . . . . . . . . . . . . . . 29 3.3.6.1 carry/borrow (c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.3.6.2 overflow (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.3.6.3 zero (z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 3.3.6.4 negative (n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.3.6.5 i-interrupt mask (i) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.3.6.6 half carry (h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 3.3.6.7 x-interrupt mask (x). . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 3.3.6.8 stop disable (s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.4 data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.5 opcodes and operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.6 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.6.1 immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.6.2 direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.6.3 extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.6.4 indexed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.6.5 inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.6.6 relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.7 instruction set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical summary mc68hc11ed0 ? rev. 1.0 central processor unit (cpu) central processor unit (cpu) 3.2 introduction this section presents information on m68hc11: central processor unit (cpu) architecture data types addressing modes instruction set special operations such as subroutine calls and interrupts the cpu is designed to treat all peripheral, input/output (i/o), and memory locations identically as addresses in the 64-kbyte memory map. this is referred to as memory-mapped i/o. i/o has no instructions separate from those used by memory. this architecture also allows accessing an operand from an external memory location with no execution time penalty. 3.3 cpu registers m68hc11 cpu registers are an integral part of the cpu and are not addressed as if they were memory locations. the seven registers, discussed in the following paragraphs, are shown in figure 3-1 . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) cpu registers mc68hc11ed0 ? rev. 1.0 technical summary central processor unit (cpu) figure 3-1. programming model 3.3.1 accumulators a, b, and d accumulators a and b are general-purpose 8-bit registers that hold operands and results of arithmetic calculations or data manipulations. for some instructions, these two accumulators are treated as a single double-byte (16-bit) accumulator called accumulator d. although most instructions can use accumulators a or b interchangeably, these exceptions apply: the abx and aby instructions add the contents of 8-bit accumulator b to the contents of 16-bit register x or y, but there are no equivalent instructions that use a instead of b. the tap and tpa instructions transfer data from accumulator a to the condition code register or from the condition code register to accumulator a. however, there are no equivalent instructions that use b rather than a. 8-bit accumulators a & b 70 70 15 0 ab d ix iy sp pc 70 c v z n i h x s or 16-bit double accumulator d index register x index register y stack pointer program counter carry/borrow from msb overflow zero negative i-interrupt mask half carry (from bit 3) x-interrupt mask stop disable condition codes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical summary mc68hc11ed0 ? rev. 1.0 central processor unit (cpu) central processor unit (cpu) the decimal adjust accumulator a (daa) instruction is used after binary-coded decimal (bcd) arithmetic operations, but there is no equivalent bcd instruction to adjust accumulator b. the add, subtract, and compare instructions associated with both a and b (aba, sba, and cba) only operate in one direction, making it important to plan ahead to ensure that the correct operand is in the correct accumulator. 3.3.2 index register x (ix) the ix register provides a 16-bit indexing value that can be added to the 8-bit offset provided in an instruction to create an effective address. the ix register can also be used as a counter or as a temporary storage register. 3.3.3 index register y (iy) the 16-bit iy register performs an indexed mode function similar to that of the ix register. however, most instructions using the iy register require an extra byte of machine code and an extra cycle of execution time because of the way the opcode map is implemented. refer to 3.5 opcodes and operands for further information. 3.3.4 stack pointer (sp) the m68hc11 cpu has an automatic program stack. this stack can be located anywhere in the address space and can be any size up to the amount of memory available in the system. normally, the sp is initialized by one of the first instructions in an application program. the stack is configured as a data structure that grows downward from high memory to low memory. each time a new byte is pushed onto the stack, the sp is decremented. each time a byte is pulled from the stack, the sp is incremented. at any given time, the sp holds the 16-bit address of the next free location in the stack. figure 3-2 is a summary of sp operations. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) cpu registers mc68hc11ed0 ? rev. 1.0 technical summary central processor unit (cpu) figure 3-2. stacking operations when a subroutine is called by a jump-to-subroutine (jsr) or branch-to- subroutine (bsr) instruction, the address of the instruction after the jsr or bsr is automatically pushed onto the stack, least significant byte first. when the subroutine is finished, a return-from-subroutine (rts) instruction is executed. the rts pulls the previously stacked return address from the stack and loads it into the program counter. execution then continues at this recovered return address. ? sp?2 stack rtn h sp?1 rtn l sp 70 pc main program $9d = jsr jsr, jump to subroutine dd next main instr. rtn direct pc main program $ad = jsr ff next main instr. rtn indexed, x pc main program $18 = pre ff next main instr. rtn indexed, y $ad = jsr pc main program $bd = pre ll next main instr. rtn indexed, y hh sp stack ccr sp+1 accb sp+2 acca sp+3 ix h sp+4 ix l sp+5 iy h sp+6 iy l sp+7 rtn h sp+8 ? sp+9 70 rtn l pc interrupt routine $3b = rti ? sp?9 stack ccr sp?8 accb sp?7 acca sp?6 ix h sp?5 ix l sp?4 iy h sp?3 iy l sp?2 rtn h sp?1 sp 70 rtn l pc main program $3f = swi pc main program $3e = wai swi, software interrupt wai, wait for interrupt rti, return from interrupt ? sp?2 stack rtn h sp?1 rtn l sp 70 pc main program $8d = bsr pc main program $39 = rts bsr, branch to subroutine rts, return from subroutine sp stack rtn h sp+1 rtn l ? sp+2 70 legend: rtn = address of next instruction in main program to be executed upon return from subroutine rtn h = most significant byte of return address rtn l = least significant byte of return address ? = stack pointer position after operation is complete dd = 8-bit direct address ($0000?$00ff) (high byte assumed to be $00) ff = 8-bit positive offset $00 (0) to $ff (255) is added to index hh = high-order byte of 16-bit extended address ll = low-order byte of 16-bit extended address rr= signed relative offset $80 (?128) to $7f (+127) (offset relative to the address following the machine code offset byte) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical summary mc68hc11ed0 ? rev. 1.0 central processor unit (cpu) central processor unit (cpu) when an interrupt is recognized, the current instruction finishes normally, the return address (the current value in the program counter) is pushed onto the stack, all of the cpu registers are pushed onto the stack, and execution continues at the address specified by the vector for the interrupt. at the end of the interrupt service routine, a return-from interrupt (rti) instruction is executed. the rti instruction causes the saved registers to be pulled off the stack in reverse order. program execution resumes at the return address. certain instructions push and pull the a and b accumulators and the x and y index registers and are often used to preserve program context. for example, pushing accumulator a onto the stack when entering a subroutine that uses accumulator a and then pulling accumulator a off the stack just before leaving the subroutine ensures that the contents of a register will be the same after returning from the subroutine as it was before starting the subroutine. 3.3.5 program counter (pc) the program counter, a 16-bit register, contains the address of the next instruction to be executed. after reset, the program counter is initialized from one of six possible vectors, depending on operating mode and the cause of reset. see table 3-1 . table 3-1. reset vector comparison mode por or reset pin clock monitor cop watchdog normal $fffe, $ffff $fffc, d $fffa, b test or boot $bffe, $bfff $bffc, d $bffa, b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) cpu registers mc68hc11ed0 ? rev. 1.0 technical summary central processor unit (cpu) 3.3.6 condition code register (ccr) this 8-bit register contains: five condition code indicators (c, v, z, n, and h), two interrupt masking bits (irq and xirq ) a stop disable bit (s) in the m68hc11 cpu, condition codes are updated automatically by most instructions. for example, load accumulator a (ldaa) and store accumulator a (staa) instructions automatically set or clear the n, z, and v condition code flags. pushes, pulls, add b to x (abx), add b to y (aby), and transfer/exchange instructions do not affect the condition codes. refer to table 3-2 , which shows what condition codes are affected by a particular instruction. 3.3.6.1 carry/borrow (c) the c bit is set if the arithmetic logic unit (alu) performs a carry or borrow during an arithmetic operation. the c bit also acts as an error flag for multiply and divide operations. shift and rotate instructions operate with and through the carry bit to facilitate multiple-word shift operations. 3.3.6.2 overflow (v) the overflow bit is set if an operation causes an arithmetic overflow. otherwise, the v bit is cleared. 3.3.6.3 zero (z) the z bit is set if the result of an arithmetic, logic, or data manipulation operation is 0. otherwise, the z bit is cleared. compare instructions do an internal implied subtraction and the condition codes, including z, reflect the results of that subtraction. a few operations (inx, dex, iny, and dey) affect the z bit and no other condition flags. for these operations, only = and conditions can be determined. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical summary mc68hc11ed0 ? rev. 1.0 central processor unit (cpu) central processor unit (cpu) 3.3.6.4 negative (n) the n bit is set if the result of an arithmetic, logic, or data manipulation operation is negative (msb = 1). otherwise, the n bit is cleared. a result is said to be negative if its most significant bit (msb) is a 1. a quick way to test whether the contents of a memory location has the msb set is to load it into an accumulator and then check the status of the n bit. 3.3.6.5 i-interrupt mask (i) the interrupt request (irq) mask (i bit) is a global mask that disables all maskable interrupt sources. while the i bit is set, interrupts can become pending, but the operation of the cpu continues uninterrupted until the i bit is cleared. after any reset, the i bit is set by default and can be cleared only by a software instruction. when an interrupt is recognized, the i bit is set after the registers are stacked, but before the interrupt vector is fetched. after the interrupt has been serviced, a return-from-interrupt instruction is normally executed, restoring the registers to the values that were present before the interrupt occurred. normally, the i bit is 0 after a return from interrupt is executed. although the i bit can be cleared within an interrupt service routine, "nesting" interrupts in this way should be done only when there is a clear understanding of latency and of the arbitration mechanism. refer to section 5. resets and interrupts . 3.3.6.6 half carry (h) the h bit is set when a carry occurs between bits 3 and 4 of the arithmetic logic unit during an add, aba, or adc instruction. otherwise, the h bit is cleared. half carry is used during bcd operations. 3.3.6.7 x-interrupt mask (x) the xirq mask (x) bit disables interrupts from the xirq pin. after any reset, x is set by default and must be cleared by a software instruction. when an xirq interrupt is recognized, the x and i bits are set after the registers are stacked, but before the interrupt vector is fetched. after the interrupt has been serviced, an rti instruction is normally executed, causing the registers to be restored to the values that were present f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) data types mc68hc11ed0 ? rev. 1.0 technical summary central processor unit (cpu) before the interrupt occurred. the x interrupt mask bit is set only by hardware (reset or xirq acknowledge). x is cleared only by program instruction (tap, where the associated bit of a is 0; or rti, where bit 6 of the value loaded into the ccr from the stack has been cleared). there is no hardware action for clearing x. 3.3.6.8 stop disable (s) setting the stop disable (s) bit prevents the stop instruction from putting the m68hc11 into a low-power stop condition. if the stop instruction is encountered by the cpu while the s bit is set, it is treated as a no-operation (nop) instruction, and processing continues to the next instruction. s is set by reset; stop is disabled by default. 3.4 data types the m68hc11 cpu supports four data types: 1. bit data 2. 8-bit and 16-bit signed and unsigned integers 3. 16-bit unsigned fractions 4. 16-bit addresses a byte is eight bits wide and can be accessed at any byte location. a word is composed of two consecutive bytes with the most significant byte at the lower value address. because the m68hc11 is an 8-bit cpu, there are no special requirements for alignment of instructions or operands. 3.5 opcodes and operands the m68hc11 family of microcontrollers uses 8-bit opcodes. each opcode identifies a particular instruction and associated addressing mode to the cpu. several opcodes are required to provide each instruction with a range of addressing capabilities. only 256 opcodes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical summary mc68hc11ed0 ? rev. 1.0 central processor unit (cpu) central processor unit (cpu) would be available if the range of values were restricted to the number able to be expressed in 8-bit binary numbers. a 4-page opcode map has been implemented to expand the number of instructions. an additional byte, called a prebyte, directs the processor from page 0 of the opcode map to one of the other three pages. as its name implies, the additional byte precedes the opcode. a complete instruction consists of a prebyte, if any, an opcode, and zero, one, two, or three operands. the operands contain information the cpu needs for executing the instruction. complete instructions can be from one to five bytes long. 3.6 addressing modes six addressing modes can be used to access memory: immediate direct extended indexed inherent relative these modes are detailed in the following paragraphs. all modes except inherent mode use an effective address. the effective address is the memory address from which the argument is fetched or stored or the address from which execution is to proceed. the effective address can be specified within an instruction, or it can be calculated. 3.6.1 immediate in the immediate addressing mode, an argument is contained in the byte(s) immediately following the opcode. the number of bytes following the opcode matches the size of the register or memory location being operated on. there are 2-, 3-, and 4- (if prebyte is required) byte f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) addressing modes mc68hc11ed0 ? rev. 1.0 technical summary central processor unit (cpu) immediate instructions. the effective address is the address of the byte following the instruction. 3.6.2 direct in the direct addressing mode, the low-order byte of the operand address is contained in a single byte following the opcode, and the high-order byte of the address is assumed to be $00. addresses $00 ? $ff are thus accessed directly, using 2-byte instructions. execution time is reduced by eliminating the additional memory access required for the high-order address byte. in most applications, this 256-byte area is reserved for frequently referenced data. in m68hc11 mcus, the memory map can be configured for combinations of internal registers, ram, or external memory to occupy these addresses. 3.6.3 extended in the extended addressing mode, the effective address of the argument is contained in two bytes following the opcode byte. these are 3-byte instructions (or 4-byte instructions if a prebyte is required). one or two bytes are needed for the opcode and two for the effective address. 3.6.4 indexed in the indexed addressing mode, an 8-bit unsigned offset contained in the instruction is added to the value contained in an index register (ix or iy). the sum is the effective address. this addressing mode allows referencing any memory location in the 64-kbyte address space. these are 2- to 5-byte instructions, depending on whether a prebyte is required. 3.6.5 inherent in the inherent addressing mode, all the information necessary to execute the instruction is contained in the opcode. operations that use only the index registers or accumulators, as well as control instructions with no arguments, are included in this addressing mode. these are 1- or 2-byte instructions. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical summary mc68hc11ed0 ? rev. 1.0 central processor unit (cpu) central processor unit (cpu) 3.6.6 relative the relative addressing mode is used only for branch instructions. if the branch condition is true, an 8-bit signed offset included in the instruction is added to the contents of the program counter to form the effective branch address. otherwise, control proceeds to the next instruction. these are usually 2-byte instructions. 3.7 instruction set refer to table 3-2 , which shows all the m68hc11 instructions in all possible addressing modes. for each instruction, the table shows the operand construction, the number of machine code bytes, and execution time in cpu e-clock cycles. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) instruction set mc68hc11ed0 ? rev. 1.0 technical summary central processor unit (cpu) table 3-2. instruction set (sheet 1 of 7) mnemonic operation description addressing instruction condition codes mode opcode operand cycles s x h i n z v c aba add accumulators a + b ? ainh1b ? 2 ?? ? ? ???? abx add b to x ix + (00 : b) ? ix inh 3a ? 3 ???????? aby add b to y iy + (00 : b) ? iy inh 18 3a ? 4 ???????? adca (opr) add with carry to a a + m + c ? a a imm adir aext a ind,x a ind,y 89 99 b9 a9 18 a9 ii dd hh ll ff ff 2 3 4 4 5 ?? ? ? ???? adcb (opr) add with carry to b b + m + c ? b b imm bdir bext b ind,x b ind,y c9 d9 f9 e9 18 e9 ii dd hh ll ff ff 2 3 4 4 5 ?? ? ? ???? adda (opr) add memory to a a + m ? a a imm adir aext a ind,x a ind,y 8b 9b bb ab 18 ab ii dd hh ll ff ff 2 3 4 4 5 ?? ? ? ???? addb (opr) add memory to b b + m ? bbimm bdir bext b ind,x b ind,y cb db fb eb 18 eb ii dd hh ll ff ff 2 3 4 4 5 ?? ? ? ???? addd (opr) add 16-bit to d d + (m : m + 1) ? dimm dir ext ind,x ind,y c3 d3 f3 e3 18 e3 jj kk dd hh ll ff ff 4 5 6 6 7 ???? ???? anda (opr) and a with memory a m ? a a imm a dir a ext a ind,x a ind,y 84 94 b4 a4 18 a4 ii dd hh ll ff ff 2 3 4 4 5 ???? ?? 0 ? andb (opr) and b with memory b m ? b b imm bdir bext b ind,x b ind,y c4 d4 f4 e4 18 e4 ii dd hh ll ff ff 2 3 4 4 5 ???? ?? 0 ? asl (opr) arithmetic shift left ext ind,x ind,y 78 68 18 68 hh ll ff ff 6 6 7 ???? ???? asla arithmetic shift left a ainh 48 ? 2 ???? ???? aslb arithmetic shift left b binh 58 ? 2 ???? ???? asld arithmetic shift left d inh 05 ? 3 ???? ???? asr arithmetic shift right ext ind,x ind,y 77 67 18 67 hh ll ff ff 6 6 7 ???? ???? asra arithmetic shift right a ainh 47 ? 2 ???? ???? asrb arithmetic shift right b binh 57 ? 2 ???? ???? bcc (rel) branch if carry clear ? c = 0 rel 24 rr 3 ???????? bclr (opr) (msk) clear bit(s) m (mm ) ? m dir ind,x ind,y 15 1d 18 1d dd mm ff mm ff mm 6 7 8 ???? ?? 0 ? c 0 b7 b0 c 0 b7 b0 c 0 b7 b0 c 0 b7 b0 a b b7 b0 c b7 b0 c b7 b0 c b7 b0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical summary mc68hc11ed0 ? rev. 1.0 central processor unit (cpu) central processor unit (cpu) bcs (rel) branch if carry set ? c = 1 rel 25 rr 3 ???????? beq (rel) branch if = zero ? z = 1 rel 27 rr 3 ???????? bge (rel) branch if ? zero ? n v = 0 rel 2c rr 3 ???????? bgt (rel) branch if > zero ? z + (n v) = 0 rel 2e rr 3 ???????? bhi (rel) branch if higher ? c + z = 0 rel 22 rr 3 ???????? bhs (rel) branch if higher or same ? c = 0 rel 24 rr 3 ???????? bita (opr) bit(s) test a with memory a m a imm adir aext a ind,x a ind,y 85 95 b5 a5 18 a5 ii dd hh ll ff ff 2 3 4 4 5 ???? ?? 0 ? bitb (opr) bit(s) test b with memory b m b imm bdir bext b ind,x b ind,y c5 d5 f5 e5 18 e5 ii dd hh ll ff ff 2 3 4 4 5 ???? ?? 0 ? ble (rel) branch if ? zero ? z + (n v) = 1 rel 2f rr 3 ???????? blo (rel) branch if lower ? c = 1 rel 25 rr 3 ???????? bls (rel) branch if lower or same ? c + z = 1 rel 23 rr 3 ???????? blt (rel) branch if < zero ? n v = 1 rel 2d rr 3 ???????? bmi (rel) branch if minus ? n = 1 rel 2b rr 3 ???????? bne (rel) branch if not = zero ? z = 0 rel 26 rr 3 ???????? bpl (rel) branch if plus ? n = 0 rel 2a rr 3 ???????? bra (rel) branch always ? 1 = 1 rel 20 rr 3 ???????? brclr(opr) (msk) (rel) branch if bit(s) clear ? m mm = 0 dir ind,x ind,y 13 1f 18 1f dd mm rr ff mm rr ff mm rr 6 7 8 ???????? brn (rel) branch never ? 1 = 0 rel 21 rr 3 ???????? brset(opr) (msk) (rel) branch if bit(s) set ? (m ) mm = 0 dir ind,x ind,y 12 1e 18 1e dd mm rr ff mm rr ff mm rr 6 7 8 ???????? bset (opr) (msk) set bit(s) m + mm ? m dir ind,x ind,y 14 1c 18 1c dd mm ff mm ff mm 6 7 8 ???? ?? 0 ? bsr (rel) branch to subroutine see figure 3-2 rel 8d rr 6 ???????? bvc (rel) branch if overflow clear ? v = 0 rel 28 rr 3 ???????? bvs (rel) branch if overflow set ? v = 1 rel 29 rr 3 ???????? cba compare a to b a ? binh11 ? 2 ???? ???? clc clear carry bit 0 ? cinh0c ? 2 ??????? 0 cli clear interrupt mask 0 ? iinh0e ? 2 ??? 0 ???? clr (opr) clear memory byte 0 ? mext ind,x ind,y 7f 6f 18 6f hh ll ff ff 6 6 7 ???? 0100 clra clear accumulator a 0 ? a a inh 4f ? 2 ???? 0100 clrb clear accumulator b 0 ? b b inh 5f ? 2 ???? 0100 clv clear overflow flag 0 ? vinh0a ? 2 ?????? 0 ? cmpa (opr) compare a to memory a ? m a imm adir aext a ind,x a ind,y 81 91 b1 a1 18 a1 ii dd hh ll ff ff 2 3 4 4 5 ???? ???? table 3-2. instruction set (sheet 2 of 7) mnemonic operation description addressing instruction condition codes mode opcode operand cycles s x h i n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) instruction set mc68hc11ed0 ? rev. 1.0 technical summary central processor unit (cpu) cmpb (opr) compare b to memory b ? m b imm bdir bext b ind,x b ind,y c1 d1 f1 e1 18 e1 ii dd hh ll ff ff 2 3 4 4 5 ???? ???? com (opr) ones complement memory byte $ff ? m ? mext ind,x ind,y 73 63 18 63 hh ll ff ff 6 6 7 ???? ?? 01 coma ones complement a $ff ? a ? a a inh 43 ? 2 ???? ?? 01 comb ones complement b $ff ? b ? b b inh 53 ? 2 ???? ?? 01 cpd (opr) compare d to memory 16-bit d ? m : m + 1 imm dir ext ind,x ind,y 1a 83 1a 93 1a b3 1a a3 cd a3 jj kk dd hh ll ff ff 5 6 7 7 7 ???? ???? cpx (opr) compare x to memory 16-bit ix ? m : m + 1 imm dir ext ind,x ind,y 8c 9c bc ac cd ac jj kk dd hh ll ff ff 4 5 6 6 7 ???? ???? cpy (opr) compare y to memory 16-bit iy ? m : m + 1 imm dir ext ind,x ind,y 18 8c 18 9c 18 bc 1a ac 18 ac jj kk dd hh ll ff ff 5 6 7 7 7 ???? ???? daa decimal adjust a adjust sum to bcd inh 19 ? 2 ???? ???? dec (opr) decrement memory byte m ? 1 ? mext ind,x ind,y 7a 6a 18 6a hh ll ff ff 6 6 7 ???? ??? ? deca decrement accumulator a a ? 1 ? a a inh 4a ? 2 ???? ??? ? decb decrement accumulator b b ? 1 ? b b inh 5a ? 2 ???? ??? ? des decrement stack pointer sp ? 1 ? sp inh 34 ? 3 ???????? dex decrement index register x ix ? 1 ? ix inh 09 ? 3 ????? ? ?? dey decrement index register y iy ? 1 ? iy inh 18 09 ? 4 ????? ? ?? eora (opr) exclusive or a with memory a m ? a a imm adir aext a ind,x a ind,y 88 98 b8 a8 18 a8 ii dd hh ll ff ff 2 3 4 4 5 ???? ?? 0 ? eorb (opr) exclusive or b with memory b m ? b b imm bdir bext b ind,x b ind,y c8 d8 f8 e8 18 e8 ii dd hh ll ff ff 2 3 4 4 5 ???? ?? 0 ? fdiv fractional divide 16 by 16 d / ix ? ix; r ? dinh 03 ? 41 ????? ??? idiv integer divide 16 by 16 d / ix ? ix; r ? dinh 02 ? 41 ????? ? 0 ? inc (opr) increment memory byte m + 1 ? mext ind,x ind,y 7c 6c 18 6c hh ll ff ff 6 6 7 ???? ??? ? inca increment accumulator a a + 1 ? a a inh 4c ? 2 ???? ??? ? table 3-2. instruction set (sheet 3 of 7) mnemonic operation description addressing instruction condition codes mode opcode operand cycles s x h i n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical summary mc68hc11ed0 ? rev. 1.0 central processor unit (cpu) central processor unit (cpu) incb increment accumulator b b + 1 ? b b inh 5c ? 2 ???? ??? ? ins increment stack pointer sp + 1 ? sp inh 31 ? 3 ???????? inx increment index register x ix + 1 ? ix inh 08 ? 3 ????? ? ?? iny increment index register y iy + 1 ? iy inh 18 08 ? 4 ????? ? ?? jmp (opr) jump see figure 3 ? 2ext ind,x ind,y 7e 6e 18 6e hh ll ff ff 3 3 4 ???????? jsr (opr) jump to subroutine see figure 3 ? 2dir ext ind,x ind,y 9d bd ad 18 ad dd hh ll ff ff 5 6 6 7 ???????? ldaa (opr) load accumulator a m ? a a imm a dir a ext a ind,x a ind,y 86 96 b6 a6 18 a6 ii dd hh ll ff ff 2 3 4 4 5 ???? ?? 0 ? ldab (opr) load accumulator b m ? b b imm b dir b ext b ind,x b ind,y c6 d6 f6 e6 18 e6 ii dd hh ll ff ff 2 3 4 4 5 ???? ?? 0 ? ldd (opr) load double accumulator d m ? a,m + 1 ? bimm dir ext ind,x ind,y cc dc fc ec 18 ec jj kk dd hh ll ff ff 3 4 5 5 6 ???? ?? 0 ? lds (opr) load stack pointer m : m + 1 ? sp imm dir ext ind,x ind,y 8e 9e be ae 18 ae jj kk dd hh ll ff ff 3 4 5 5 6 ???? ?? 0 ? ldx (opr) load index register x m : m + 1 ? ix imm dir ext ind,x ind,y ce de fe ee cd ee jj kk dd hh ll ff ff 3 4 5 5 6 ???? ?? 0 ? ldy (opr) load index register y m : m + 1 ? iy imm dir ext ind,x ind,y 18 ce 18 de 18 fe 1a ee 18 ee jj kk dd hh ll ff ff 4 5 6 6 6 ???? ?? 0 ? lsl (opr) logical shift left ext ind,x ind,y 78 68 18 68 hh ll ff ff 6 6 7 ???? ???? lsla logical shift left a ainh 48 ? 2 ???? ???? lslb logical shift left b binh 58 ? 2 ???? ???? lsld logical shift left double inh 05 ? 3 ???? ???? lsr (opr) logical shift right ext ind,x ind,y 74 64 18 64 hh ll ff ff 6 6 7 ???? 0 ??? lsra logical shift right a ainh 44 ? 2 ???? 0 ??? table 3-2. instruction set (sheet 4 of 7) mnemonic operation description addressing instruction condition codes mode opcode operand cycles s x h i n z v c c 0 b7 b0 c 0 b7 b0 c 0 b7 b0 c 0 b7 b0 a b b7 b0 c 0 b7 b0 c 0 b7 b0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) instruction set mc68hc11ed0 ? rev. 1.0 technical summary central processor unit (cpu) lsrb logical shift right b binh 54 ? 2 ???? 0 ??? lsrd logical shift right double inh 04 ? 3 ???? 0 ??? mul multiply 8 by 8 a ? b ? dinh3d ? 10 ??????? ? neg (opr) two ? s complement memory byte 0 ? m ? mext ind,x ind,y 70 60 18 60 hh ll ff ff 6 6 7 ???? ???? nega two ? s complement a 0 ? a ? a a inh 40 ? 2 ???? ???? negb two ? s complement b 0 ? b ? b b inh 50 ? 2 ???? ???? nop no operation no operation inh 01 ? 2 ???????? oraa (opr) or accumulator a (inclusive) a + m ? a a imm adir aext a ind,x a ind,y 8a 9a ba aa 18 aa ii dd hh ll ff ff 2 3 4 4 5 ???? ?? 0 ? orab (opr) or accumulator b (inclusive) b + m ? b b imm bdir bext b ind,x b ind,y ca da fa ea 18 ea ii dd hh ll ff ff 2 3 4 4 5 ???? ?? 0 ? psha push a onto stack a ? stk,sp = sp ? 1 a inh 36 ? 3 ???????? pshb push b onto stack b ? stk,sp = sp ? 1 b inh 37 ? 3 ???????? pshx push x onto stack (lo first) ix ? stk,sp = sp ? 2 inh 3c ? 4 ???????? pshy push y onto stack (lo first) iy ? stk,sp = sp ? 2 inh 18 3c ? 5 ???????? pula pull a from stack sp = sp + 1, a ? stk a inh 32 ? 4 ???????? pulb pull b from stack sp = sp + 1, b ? stk b inh 33 ? 4 ???????? pulx pull x from stack (hi first) sp = sp + 2, ix ? stk inh 38 ? 5 ???????? puly pull y from stack (hi first) sp = sp + 2, iy ? stk inh 18 38 ? 6 ???????? rol (opr) rotate left ext ind,x ind,y 79 69 18 69 hh ll ff ff 6 6 7 ???? ???? rola rotate left a a inh 49 ? 2 ???? ???? rolb rotate left b b inh 59 ? 2 ???? ???? ror (opr) rotate right ext ind,x ind,y 76 66 18 66 hh ll ff ff 6 6 7 ???? ???? rora rotate right a a inh 46 ? 2 ???? ???? rorb rotate right b b inh 56 ? 2 ???? ???? rti return from interrupt see figure 3 ? 2inh 3b ? 12 ??????? table 3-2. instruction set (sheet 5 of 7) mnemonic operation description addressing instruction condition codes mode opcode operand cycles s x h i n z v c c 0 b7 b0 c 0 b7 b0 a b b7 b0 c b7 b0 c b7 b0 c b7 b0 c b7 b0 c b7 b0 c b7 b0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical summary mc68hc11ed0 ? rev. 1.0 central processor unit (cpu) central processor unit (cpu) rts return from subroutine see figure 3-2 inh 39 ? 5 ???????? sba subtract b from a a ? b ? ainh10 ? 2 ???? ???? sbca (opr) subtract with carry from a a ? m ? c ? a a imm adir aext a ind,x a ind,y 82 92 b2 a2 18 a2 ii dd hh ll ff ff 2 3 4 4 5 ???? ???? sbcb (opr) subtract with carry from b b ? m ? c ? b b imm bdir bext b ind,x b ind,y c2 d2 f2 e2 18 e2 ii dd hh ll ff ff 2 3 4 4 5 ???? ???? sec set carry 1 ? cinh0d ? 2 ??????? 1 sei set interrupt mask 1 ? iinh0f ? 2 ??? 1 ???? sev set overflow flag 1 ? vinh0b ? 2 ?????? 1 ? staa (opr) store accumulator a a ? madir aext a ind,x a ind,y 97 b7 a7 18 a7 dd hh ll ff ff 3 4 4 5 ???? ?? 0 ? stab (opr) store accumulator b b ? mbdir bext b ind,x b ind,y d7 f7 e7 18 e7 dd hh ll ff ff 3 4 4 5 ???? ?? 0 ? std (opr) store accumulator d a ? m, b ? m + 1 dir ext ind,x ind,y dd fd ed 18 ed dd hh ll ff ff 4 5 5 6 ???? ?? 0 ? stop stop internal clocks ? inh cf ? 2 ???????? sts (opr) store stack pointer sp ? m : m + 1 dir ext ind,x ind,y 9f bf af 18 af dd hh ll ff ff 4 5 5 6 ???? ?? 0 ? stx (opr) store index register x ix ? m : m + 1 dir ext ind,x ind,y df ff ef cd ef dd hh ll ff ff 4 5 5 6 ???? ?? 0 ? sty (opr) store index register y iy ? m : m + 1 dir ext ind,x ind,y 18 df 18 ff 1a ef 18 ef dd hh ll ff ff 5 6 6 6 ???? ?? 0 ? suba (opr) subtract memory from a a ? m ? aaimm adir aext a ind,x a ind,y 80 90 b0 a0 18 a0 ii dd hh ll ff ff 2 3 4 4 5 ???? ???? subb (opr) subtract memory from b b ? m ? baimm adir aext a ind,x a ind,y c0 d0 f0 e0 18 e0 ii dd hh ll ff ff 2 3 4 4 5 ???? ???? subd (opr) subtract memory from d d ? m : m + 1 ? dimm dir ext ind,x ind,y 83 93 b3 a3 18 a3 jj kk dd hh ll ff ff 4 5 6 6 7 ???? ???? swi software interrupt see figure 3 ? 2inh 3f ? 14 ??? 1 ???? tab transfer a to b a ? binh16 ? 2 ???? ?? 0 ? tap transfer a to cc register a ? ccr inh 06 ? 2 ??????? tba transfer b to a b ? ainh17 ? 2 ???? ?? 0 ? table 3-2. instruction set (sheet 6 of 7) mnemonic operation description addressing instruction condition codes mode opcode operand cycles s x h i n z v c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) instruction set mc68hc11ed0 ? rev. 1.0 technical summary central processor unit (cpu) test test (only in test modes) address bus counts inh 00 ? * ???????? tpa transfer cc register to a ccr ? ainh07 ? 2 ???????? tst (opr) test for zero or minus m ? 0 ext ind,x ind,y 7d 6d 18 6d hh ll ff ff 6 6 7 ???? ?? 00 tsta test a for zero or minus a ? 0 a inh 4d ? 2 ???? ?? 00 tstb test b for zero or minus b ? 0 b inh 5d ? 2 ???? ?? 00 tsx transfer stack pointer to x sp + 1 ? ix inh 30 ? 3 ???????? tsy transfer stack pointer to y sp + 1 ? iy inh 18 30 ? 4 ???????? txs transfer x to stack pointer ix ? 1 ? sp inh 35 ? 3 ???????? tys transfer y to stack pointer iy ? 1 ? sp inh 18 35 ? 4 ???????? wai wait for interrupt stack regs & wait inh 3e ? ** ???????? xgdx exchange d with x ix ? d, d ? ix inh 8f ? 3 ???????? xgdy exchange d with y iy ? d, d ? iy inh 18 8f ? 4 ???????? table 3-2. instruction set (sheet 7 of 7) mnemonic operation description addressing instruction condition codes mode opcode operand cycles s x h i n z v c cycle * infinity or until reset occurs ** 12 cycles are used beginning with the opcode fetch. a wait state is entered which remains in effect for an integer number of mpu e-clock cycles (n) until an interrupt is recognized. finally, two additional cycles are used to fetch the appropriate interrupt vector (14 + n total). operands dd = 8-bit direct address ($0000 ? $00ff) (high byte assumed to be $00) ff = 8-bit positive offset $00 (0) to $ff (255) (is added to index) hh = high-order byte of 16-bit extended address ii = one byte of immediate data jj = high-order byte of 16-bit immediate data kk = low-order byte of 16-bit immediate data ll = low-order byte of 16-bit extended address mm = 8-bit mask (set bits to be affected) rr = signed relative offset $80 ( ? 128) to $7f (+127) (offset relative to address following machine code offset byte)) operators ( ) contents of register shown inside parentheses ? is transferred to ? is pulled from stack ? is pushed onto stack boolean and + arithmetic addition symbol except where used as inclusive-or symbol in boolean formula exclusive-or ? multiply : concatenation ? arithmetic subtraction symbol or negation symbol (two ? s complement) condition codes ? bit not changed 0 bit always cleared 1bit always set ? bit cleared or set, depending on operation bit can be cleared, cannot become set f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical summary mc68hc11ed0 ? rev. 1.0 central processor unit (cpu) central processor unit (cpu) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc11ed0 ? rev. 1.0 te c h n i c a l s u m m a r y operating modes and on-chip memory technical data ? mc68hc11ed0 section 4. operating modes and on-chip memory 4.1 contents 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.3 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.3.1 bootstrap mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.3.2 special test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.3.3 expanded operating mode . . . . . . . . . . . . . . . . . . . . . . . . .45 4.4 mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.5 on-chip memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.5.1 memory map and register block . . . . . . . . . . . . . . . . . . . . .49 4.5.2 ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 4.2 introduction the mc68hc11ed0 microcontroller (mcu) has three modes of operation. for expanded and special test modes, there are no reset or interrupt vectors contained in on-chip resources. an external memory must be used to provide vectors at locations $ffc0 ? $ffff. in bootstrap mode, a small on-chip read-only memory (rom) becomes present in the memory map and provides the vectors for this mode. refer to figure 4-3 . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical summary mc68hc11ed0 ? rev. 1.0 operating modes and on-chip memory operating modes and on-chip memory 4.3 operating modes this subsection describes the three memory modes: bootstrap mode special test mode expanded operating mode refer to figure 4-3 . 4.3.1 bootstrap mode bootstrap mode allows special-purpose programs to be entered into internal random-access memory (ram). the mcu contains 256 bytes of bootstrap rom which is enabled and present in the memory map only when the device is in bootstrap mode. the bootstrap rom contains a small program which initializes the serial communications interface (sci) and allows the user to download exactly 256 bytes of code into on-chip ram. after receiving the character for address $01ff, control passes to the loaded program at $0100. vectors are present on chip and located at $bfc0 ? $bfff. 4.3.2 special test mode special test mode is used primarily for factory testing. in this operating mode, vectors must be provided externally at $bfc0 ? $bfff. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . operating modes and on-chip memory operating modes mc68hc11ed0 ? rev. 1.0 technical summary operating modes and on-chip memory 4.3.3 expanded operating mode in expanded operating mode, the mcu has a 64-kbyte address range and, using the expansion bus, can access external resources within the 64-kbyte space. this space includes: on-chip memory addresses addressing capabilities for external peripheral and memory devices in expanded operating mode, high-order address bits are output on addr[15:8] pins, low-order address bits and the data bus are multiplexed on addr/data[7:0]. refer to figure 1-1. mc68hc11ed0 block diagram . the read/write (r/w ) and address strobe (as) signals allow the low-order address and the 8-bit data bus to be time-multiplexed on the same pins. during the first half of each bus cycle, address information is present. during the second half of each bus cycle, the pins become the bidirectional data bus. as is an active-high latch enable signal for an external address latch. address information is allowed through the transparent latch while as is high and is latched when as drives low. the address, r/w , and as signals are active and valid for all bus cycles including accesses to internal memory locations. the e clock is used to enable external devices to drive data onto the internal data bus during the second half of a read bus cycle (e clock high). r/w controls the direction of data transfers. r/w drives low when data is being written to the external data bus. r/w will remain low during consecutive data bus write cycles, such as when a double-byte store occurs. refer to figure 4-1 for an example of address and data multiplexing. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical summary mc68hc11ed0 ? rev. 1.0 operating modes and on-chip memory operating modes and on-chip memory figure 4-1. address and data demultiplexing 4.4 mode selection operating modes are selected by a combination of logic levels applied to two input pins (moda and modb) during reset. the logic level present (at the rising edge of reset) on these inputs is reflected in bits in the highest priority i-bit interrupt and miscellaneous (hprio) register. after reset, the operating mode may be changed as shown in figure 4-2 . mc54/74hc373 mcu addr14 addr13 addr12 addr11 addr10 addr9 addr8 addr15 addr6 addr5 addr4 addr3 addr2 addr1 addr0 addr7 data6 data5 data4 data3 data2 data1 data0 data7 data2 data3 data4 data5 data6 data7 data8 data1 q2 q3 q4 q5 q6 q7 q8 q1 q0 le addr6/data6 addr5/data5 addr4/data4 addr3/data3 addr2/data2 addr1/data1 addr0/data0 addr7/data7 as addr14 addr13 addr12 addr11 addr10 addr9 addr8 addr15 r/w e we f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . operating modes and on-chip memory mode selection mc68hc11ed0 ? rev. 1.0 technical summary operating modes and on-chip memory rboot ? read bootstrap rom bit valid only when smod is set (bootstrap or special test mode); can be written only in special modes 0 = bootloader rom disabled and not in map 1 = bootloader rom enabled and in map at $be00 ? $bfff smod and mda ? special mode select and mode select a bits the initial value of smod is the inverse of the logic level present on the modb pin at the rising edge of reset. the initial value of mda equals the logic level present on the moda pin at the rising edge of reset. these two bits can be read at any time. they can be written any time in special modes. mda can be written only once in normal modes. smod cannot be set once it has been cleared. caution: unlike other m68hc11 family devices, the mc68hc11ed0 will not function in single-chip operating mode. if moda is pulled low and modb is pulled high at the rising edge of reset (the condition that causes most address: $003c bit 7 6 5 4 3 2 1 bit 0 read: rboot (1) smod (1) mda (1) irvne (1) psel3 psel2 psel1 psel0 write: resets: expanded: bootstrap: special test: 0 1 0 0 1 1 1 0 1 0 0 1 0 0 0 1 1 1 0 0 0 1 1 1 1. the reset values depend on the mode selected at power-up. figure 4-2. highest priority i-bit interrupt and miscellaneous register (hprio) input mode latched at reset modb moda smod mda 10 high-impedance state addr/data (cpu held in reset) 00 1 1 expanded 0 1 0 0 bootstrap 1 0 0 1 special test 1 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical summary mc68hc11ed0 ? rev. 1.0 operating modes and on-chip memory operating modes and on-chip memory m68hc11 devices to enter single-chip mode) the cpu will remain in reset until the reset pin is pulled low then released with appropriate logic levels applied to moda and modb. irvne ? internal read visibility/not e bit irvne can be written once in any mode. in special test mode, irvne is reset to 1. in all other modes, irvne is reset to 0. in expanded test modes, irvne determines whether internal read visibility (irv) is on or off. 0 = no internal read visibility on external bus 1 = data from internal reads driven out the external data bus in bootstrap mode, irvne determines whether the e clock drives out from the chip. 0 = e driven out from the chip 1 = e pin driven low psel[3:0] ? priority select bits refer to section 5. resets and interrupts . 4.5 on-chip memory the mc68hc11ed0 contains 512 bytes of on-chip static ram. there is no on-chip rom. since the mc68hc11ed0 is intended for expanded mode applications only, reset and interrupt vectors are not contained in on-chip resources. an external memory must provide these at locations $ffc0 ? $ffff. refer to figure 4-3 . mode irvne out of reset e clock out of reset irv out of reset irvne affects only irvne can be written expanded 0 on off irv once bootstrap 0 on off e once special test 1 on on irv once f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . operating modes and on-chip memory on-chip memory mc68hc11ed0 ? rev. 1.0 technical summary operating modes and on-chip memory 4.5.1 memory map and register block the init register controls the location of the register block and ram in the 64-kbyte central processor unit (cpu) address space. the 64-kbyte register block originates at $0000 after reset and can be placed at any 4-kbyte boundary ($x000) by writing an appropriate value to the init register. since the ram also begins at $0000 after reset, 64 bytes are overlaid by the register block. registers are a higher priority resource than ram. therefore, the ram which is overlaid by registers is inaccessible. either the registers or the ram must be remapped to gain access to all 512 bytes of the ram. refer to figure 4-3 and figure 4-4 . figure 4-3. mc68hc11ed0 memory map $ffc0 $ffff normal mode interrupt vectors external 448 bytes ram (1) 64-byte register block (1) bootstrap special test $0000 $0200 $ffc0 $ffff $0000 $0040 $103f $bf00 expanded $bfff $bfc0 $bfff special modes interrupt vectors boot rom ext ext $003f ext $0040 $01ff ext ext can be remapped to any 4-k page by the init register can be remapped to any 4-k page by the init register note 1. to access the full 512 bytes of ram, remap either the register block or the ram to any 4-k ($x000) boundary. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical summary mc68hc11ed0 ? rev. 1.0 operating modes and on-chip memory operating modes and on-chip memory addr. register name bit 7 6 5 4 3 2 1 bit 0 $0000 port a data register (porta) see page 66. read: pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 write: reset: u 0 0 0 u u u u $0001 reserved r r r r r r r r $0007 reserved r r r r r r r r $0008 port d data register (portd) see page 68. read: pd5 pd4 pd3 pd2 pd1 pd0 write: reset: 0 0 u u u u u u $0009 port d data direction register (ddrd) see page 69. read: ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 write: reset: 0 0 0 0 0 0 0 0 $000a reserved r r r r r r r r $000b timer compare force register (cforc) see page 91. read: foc1 foc2 foc3 foc4 foc5 write: reset: 0 0 0 0 0 0 0 0 $000c output compare 1 mask register (oc1m) see page 92. read: oc1m7 oc1m6 oc1m5 oc1m4 oc1m3 write: reset: 0 0 0 0 0 0 0 0 $000d output compare 1 data register (oc1d) see page 92. read: oc1d7 oc1d6 oc1d5 oc1d4 oc1d3 write: reset: 0 0 0 0 0 0 0 0 $000e timer count register high (tcnt) see page 93. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 = unimplemented r = reserved u = unaffected figure 4-4. register and control bit assignments (sheet 1 of 6) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . operating modes and on-chip memory on-chip memory mc68hc11ed0 ? rev. 1.0 technical summary operating modes and on-chip memory $000f timer count register low (tcnt) see page 93. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $0010 timer input capture register 1 high (tic1) see page 94. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: unaffected by reset $0011 timer input capture register 1 low (tic1) see page 94. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: unaffected by reset $0012 timer input capture register 2 high (tic2) see page 94. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: unaffected by reset $0013 timer input capture register 2 low (tic2) see page 94. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: unaffected by reset $0014 timer input capture register 3 high (tic3) see page 94. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: unaffected by reset $0015 timer input capture register 3 low (tic3) see page 94. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: unaffected by reset $0016 timer output compare register 1 high (toc1) see page 95. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 1 1 1 1 1 1 1 1 $0017 timer output compare register 1 low (toc1) see page 95. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 1 1 1 1 1 1 1 1 addr. register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented r = reserved u = unaffected figure 4-4. register and control bit assignments (sheet 2 of 6) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical summary mc68hc11ed0 ? rev. 1.0 operating modes and on-chip memory operating modes and on-chip memory $0018 timer output compare register 2 high (toc2) see page 95. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 1 1 1 1 1 1 1 1 $0019 timer output compare register 2 low (toc2) see page 95. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 1 1 1 1 1 1 1 1 $001a timer output compare register 3 high (toc3) see page 95. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 1 1 1 1 1 1 1 1 $001b timer output compare register 3 low (toc3) see page 95. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 1 1 1 1 1 1 1 1 $001c timer output compare register 4 high (toc4) see page 96. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 1 1 1 1 1 1 1 1 $001d timer output compare register 4 low (toc4) see page 96. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 1 1 1 1 1 1 1 1 $001e timer input capture4/output compare 5 high (ti4/o5) see page 96. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 1 1 1 1 1 1 1 1 $001f timer input capture4/output compare 5 low (ti4/o5) see page 96. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 1 1 1 1 1 1 1 1 $0020 timer control register 1 (tctl1) see page 97. read: om2 ol2 om3 ol3 om4 ol4 om5 ol5 write: reset: 0 0 0 0 0 0 0 0 addr. register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented r = reserved u = unaffected figure 4-4. register and control bit assignments (sheet 3 of 6) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . operating modes and on-chip memory on-chip memory mc68hc11ed0 ? rev. 1.0 technical summary operating modes and on-chip memory $0021 timer control register 2 (tctl2) see page 98. read: edg4b edg4a edg1b edg1a edg2b edg2a edg3b edg3a write: reset: 0 0 0 0 0 0 0 0 $0022 timer interrupt mask 1 register (tmsk1) see page 99. read: oc1i oc2i oc3i oc4i i4/o5i ic1i ic2i ic3i write: reset: 0 0 0 0 0 0 0 0 $0023 timer interrupt flag 1 register (tflg1) see page 100. read: oc1f oc2f oc3f oc4f i4/o5f ic1f ic2f ic3f write: reset: 0 0 0 0 0 0 0 0 $0024 timer interrupt mask 2 register (tmsk2) see page 100. read: toi rtii paovi paii pr1 pr0 write: reset: 0 0 0 0 0 0 0 0 $0025 timer interrupt flag 2 register (tflg2) see page 102. read: tof rtif paovf paif write: reset: 0 0 0 0 0 0 0 0 $0026 pulse accumulator control register (pactl) see page 104. read: ddra7 paen pamod pedge ddra3 i4/o5 rtr1 rtr0 write: reset: 0 0 0 0 0 0 0 0 $0027 pulse accumulator counter register (pacnt) see page 106. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: unaffected by reset $0028 serial peripheral control register (spcr) see page 83. read: spie spe dwom mstr cpol cpha spr1 spr0 write: reset: 0 0 0 0 0 1 0 0 $0029 serial peripheral status register (spsr) see page 85. read: spif wcol modf write: reset: 0 0 0 0 0 0 0 0 addr. register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented r = reserved u = unaffected figure 4-4. register and control bit assignments (sheet 4 of 6) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical summary mc68hc11ed0 ? rev. 1.0 operating modes and on-chip memory operating modes and on-chip memory $002a spi data register i/o (spdr) see page 86. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset $002b baud rate register (baud) see page 74. read: tclr scp1 scp0 rckb scr2 scr1 scr0 write: reset: 0 0 0 0 0 u u u $002c sci control register 1 (sccr1) see page 77. read: r8 t8 m wake write: reset: 0 0 0 0 0 0 0 0 $002d sci control register 2 (sccr2) see page 78. read: tie tcie rie ilie te re rwu sbk write: reset: 0 0 0 0 0 0 0 0 $002e sci status register (scsr) see page 79. read: tdre tc rdrf idle or nf fe write: reset: 1 1 0 0 0 0 0 0 $002f sci data register (scdr) see page 80. read: r7/t7 r6/t6 r5/t5 r4/t4 r3/t3 r2/t2 r1/t1 r0/t0 write: reset: unaffected by reset $0030 reserved r r r r r r r r $0038 reserved r r r r r r r r $0039 system configuration options register (option) see page 60. read: irqe (1) dly (1) cme cr1 (1) cr0 (1) write: reset: 0 0 0 1 0 0 0 0 note 1. can be written only once in the first 64 cycles out of reset in normal modes or at any time in special modes. addr. register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented r = reserved u = unaffected figure 4-4. register and control bit assignments (sheet 5 of 6) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . operating modes and on-chip memory on-chip memory mc68hc11ed0 ? rev. 1.0 technical summary operating modes and on-chip memory $003a arm/reset cop timer circuitry register (coprst) see page 61. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $003b reserved r r r r r r r r $003c highest priority i-bit interrupt and miscellaneous register (hprio) see page 63. read: rboot smod mda irvne (1) psel3 psel2 psel1 psel0 write: reset: note 1 note 1 note 1 u 0 1 0 1 note 1. rboot, smod, and mda reset depends on power-up initialization mode and can be written only in special mode. $003d ram and register mapping register (init) see page 56. read: ram3 ram2 ram1 ram0 reg3 reg2 reg1 reg0 write: reset: 0 0 0 0 0 0 0 0 $003e reserved r r r r r r r r $003f system configuration register (config) see page 62. read: nocop write: reset: 0 0 0 0 0 0 0 0 addr. register name bit 7 6 5 4 3 2 1 bit 0 = unimplemented r = reserved u = unaffected figure 4-4. register and control bit assignments (sheet 6 of 6) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical summary mc68hc11ed0 ? rev. 1.0 operating modes and on-chip memory operating modes and on-chip memory 4.5.2 ram the mc68hc11ed0 has 512 bytes of on-chip static ram. the ram can be mapped to any 4-kbyte boundary. upon reset, the ram is mapped at $0000 ? $01ff. the register block also begins at $0000 and overlaps the ram space. since registers have priority over ram, this causes 64 bytes of ram to be lost. however, the user can map either the ram or the register block to any 4-kbyte boundary ($x000) and access the full 512 bytes of ram. remapping is accomplished by writing appropriate values to the init register. when power is removed form the mcu, ram contents may be preserved using the modb/v stby pin. a 4-volt nominal power source applied to this pin protects all 512 bytes of ram. note: init can be written only once in the first 64-cycles out of reset in normal modes or at any time in special modes. ram[3:0] ? internal ram map position bits these bits determine the upper four bits of the ram address. at reset ram is mapped to $0000 and includes the register block. refer to figure 4-3 . reg[3:0] ? 128-byte register block map position bits these bits determine the upper four bits of the register space address. at reset registers are mapped to $0000 and overwrite the first 64 bytes of ram. refer to figure 4-3 . address: $003d bit 7654321bit 0 read: ram3 ram2 ram1 ram0 reg3 reg2 reg1 reg0 write: reset:00000000 figure 4-5. ram and register mapping register (init) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc11ed0 ? rev. 1.0 te c h n i c a l s u m m a r y resets and interrupts technical data ? mc68hc11ed0 section 5. resets and interrupts 5.1 contents 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.3 resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.4 system configuration options register . . . . . . . . . . . . . . . . . . 60 5.5 arm/reset cop timer circuitry register . . . . . . . . . . . . . . . . . 61 5.6 configuration control register . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.7 highest priority i-bit interrupt and miscellaneous register. . . . . . . . . . . . . . . . . . . . . . . . . 63 5.2 introduction this section describes the mc68hc11ed0 reset and interrupt structure. 5.3 resets the mc68hc11ed0 has three reset vectors and 18 interrupt vectors. the reset vectors are: reset or power-on reset clock monitor fail computer operating properly (cop) failure f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical summary mc68hc11ed0 ? rev. 1.0 resets and interrupts resets and interrupts the 18 interrupt vectors service 22 interrupt sources (three non-maskable, 19 maskable). the three non-maskable interrupt sources are: xirq pin (x-bit interrupt) illegal opcode trap software interrupt on-chip peripheral systems generate maskable interrupts, which are recognized only if the global interrupt mask bit (i) in the condition code register (ccr) is clear. maskable interrupts are prioritized according to a default arrangement; however, any one source can be elevated to the highest maskable priority position by a software-accessible control register (hprio). hprio can be written at any time, provided bit i in the ccr is set. nineteen interrupt sources in the mc68hc11ed0 are subject to masking by the global interrupt mask bit (bit i in the ccr). in addition to the global i bit, all of these sources, except the external interrupt (irq ) pin, are controlled by local enable bits in the control registers. most interrupt sources in m68hc11 devices have separate interrupt vectors; therefore there is usually no need for software to poll control registers to determine the cause of an interrupt. for some interrupt sources, such as the serial communications interface (sci) interrupts, the flags are automatically cleared during the normal course of responding to the interrupt requests. for example, the rdrf flag in the sci system is cleared by the automatic clearing mechanism invoked by a read of the sci status register while rdrf is set, followed by a read of the sci data register. the normal response to an rdrf interrupt request would be to read the sci status register to check for receive errors, then to read the received data from the sci data register. these two steps satisfy the automatic clearing mechanism without requiring any special instructions. refer to table 5-1 for interrupt and reset vector assignments. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets and interrupts resets mc68hc11ed0 ? rev. 1.0 technical summary resets and interrupts 1. same level as an instruction table 5-1. interrupt and reset vector assignments vector address interrupt source ccr mask bit local mask priority (1 = high) $ffc0, $ffc1 ? $ffd4, $ffd5 reserved ?? ? $ffd6, $ffd7 sci serial system: sci receive data register full sci receiver overrun sci transmit data register empty sci transmit complete sci idle line detect i rie rie tie tcie ilie 19 20 21 22 23 $ffd8, $ffd9 spi serial transfer complete i spie 18 $ffda, $ffdb pulse accumulator input edge i paii 17 $ffdc, $ffdd pulse accumulator overflow i paovi 16 $ffde, $ffdf timer overflow i toi 15 $ffe0, $ffe1 timer input capture 4/output compare 5 i i4/o5i 14 $ffe2, $ffe3 timer output compare 4 i oc4i 13 $ffe4, $ffe5 timer output compare 3 i oc3i 12 $ffe6, $ffe7 timer output compare 2 i oc2i 11 $ffe8, $ffe9 timer output compare 1 i oc1i 10 $ffea, $ffeb timer input capture 3 i ic3i 9 $ffec, $ffed timer input capture 2 i ic2i 8 $ffee, $ffef timer input capture 1 i ic1i 7 $fff0, $fff1 real-time interrupt i rtii 6 $fff2, $fff3 irq (external pin) i none 5 $fff4, $fff5 xirq pin x none 4 $fff6, $fff7 software interrupt none none note 1 $fff8, $fff9 illegal opcode trap none none note 1 $fffa, $fffb cop failure none nocop 3 $fffc, $fffd clock monitor fail none cme 2 $fffe, $ffff reset none none 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical summary mc68hc11ed0 ? rev. 1.0 resets and interrupts resets and interrupts 5.4 system configuration options register refer to figure 5-1 for a description of the system configuration options register (option) bits [7:6] ? unimplemented always read as 0 irqe ? irq select edge sensitive only bit 0 = low level recognition 1 = falling edge recognition dly ? enable oscillator startup delay on exit from stop mode bit 0 = no stabilization delay on exit from stop mode 1 = stabilization delay enabled on exit from stop mode cme ? clock monitor enable bit 0 = clock monitor disabled; slow clocks can be used 1 = slow or stopped clocks cause clock failure reset. bit 2 ? unimplemented always reads 0 cr[1:0] ? cop timer rate select bit refer to description of the nocop bit in 5.6 configuration control register . address: $0039 bit 7654321bit 0 read: irqe (1) dly (1) cme cr1 (1) cr0 (1) write: reset:00010000 note 1. can be written only once in the first 64 cycles out of reset in normal modes or at any time in special modes. = unimplemented figure 5-1. system configuration options register (option) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets and interrupts arm/reset cop timer circuitry register mc68hc11ed0 ? rev. 1.0 technical summary resets and interrupts 5.5 arm/reset cop timer circuitry register refer to figure 5-2 for a description of the arm/reset cop timer circuitry register (coprst). write $55 to coprst to arm cop watchdog clearing mechanism. write $aa to coprst to reset cop watchdog. refer to description of the nocop bit in 5.6 configuration control register . table 5-2. cop timer rate select cr[1:0] rate selected xtal = 4.0 mhz timeout ? 0 ms, + 32.8 ms xtal = 8.0 mhz timeout ? 0 ms, + 16.4 ms xtal = 12.0 mhz timeout ? 0 ms, + 10.9 ms 0 0 2 15 e 32.768 ms 16.384 ms 10.923 ms 0 1 2 17 e 131.07 ms 65.536 ms 43.691 ms 1 0 2 19 e 524.29 ms 262.14 ms 174.76 ms 1 1 2 21 e 2.1 s 1.049 s 699.05 ms e = 1.0 mhz 2.0 mhz 3.0 mhz address: $003a bit 7654321bit 0 read: bit 7bit 6bit 6bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 figure 5-2. arm/reset cop timer circuitry register (coprst) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical summary mc68hc11ed0 ? rev. 1.0 resets and interrupts resets and interrupts 5.6 configuration control register in many m68hc11 devices the configuration control register (config) is used to define various system functions. in the mc68hc11ed0, config controls only one microcontroller (mcu) function. the nopcop bit disables the cop watchdog circuit when it is set. refer to table 5-2 and figure 5-3 . bits [7:3] ? unimplemented always read as 0 nocop ? cop system disable bit resets to programmed value 0 = cop enabled (forces reset on timeout) 1 = cop disabled (does not force reset on timeout) bits [1:0] ? unimplemented always read as 0 address: $003f bit 7 6 5 4 3 2 1 bit 0 read: nocop (1) write: reset states: expanded mode special test mode bootstrap mode 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1. nocop must be written during the first 64 cycles after reset in normal modes (smod = 0) or at any time in special modes (smod = 1). = unimplemented figure 5-3. system configuration register (config) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets and interrupts highest priority i-bit interrupt and miscellaneous register mc68hc11ed0 ? rev. 1.0 technical summary resets and interrupts 5.7 highest priority i-bit interrupt and miscellaneous register rboot ? read bootstrap rom bit refer to section 4. operating modes and on-chip memory . smod ? special mode select bit refer to section 4. operating modes and on-chip memory . mda ? mode select a bit refer to section 4. operating modes and on-chip memory . irvne ? internal read visibility/not e bit refer to section 4. operating modes and on-chip memory . psel[3:0] ? priority select bits can be written only while the i bit in the ccr is set (interrupts disabled). these bits select one interrupt source to be elevated above all other i bit related sources. see table 5-3 . address: $003c bit 7654321bit 0 read: rboot (1) smod (1) mda (1) irvne psel3 psel2 psel1 psel0 write: reset:uuuu 0101 1. rboot, smod, and mda reset depends on power-up initialization mode and can only be written only in special mode. u = undefined figure 5-4. highest priority i-bit interrupt and miscellaneous register (hprio) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical summary mc68hc11ed0 ? rev. 1.0 resets and interrupts resets and interrupts table 5-3. highest priority interrupt selection psel[3:0] interrupt source promoted 0 0 0 0 timer overflow 0 0 0 1 pulse accumulator overflow 0 0 1 0 pulse accumulator input edge 0 0 1 1 spi serial transfer complete 0 1 0 0 sci serial system 0 1 0 1 reserved (default to irq ) 0 1 1 0 irq (external pin) 0 1 1 1 real-time interrupt 1 0 0 0 timer input capture 1 1 0 0 1 timer input capture 2 1 0 1 0 timer input capture 3 1 0 1 1 timer output compare 1 1 1 0 0 timer output compare 2 1 1 0 1 timer output compare 3 1 1 1 0 timer output compare 4 1 1 1 1 timer input capture 4/output compare 5 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc11ed0 ? rev. 1.0 te c h n i c a l s u m m a r y parallel input/output (i/o) ports technical data ? mc68hc11ed0 section 6. parallel input/output (i/o) ports 6.1 contents 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.3 port a data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.4 pulse accumulator control register. . . . . . . . . . . . . . . . . . . . . 67 6.5 port d data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.6 port d data direction register . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.2 introduction the mc68hc11ed0 has up to 14 input/output (i/o) lines. the address/data bus of this microcontroller (mcu) is multiplexed and has no i/o ports associated with it. table 6-1 provides a summary of the configuration and features of each port. note: do not confuse pin function with the electrical state of the pin at reset. all general-purpose i/o pins configured as inputs at reset are in a high-impedance state and the contents of port data registers is undefined. in port descriptions, a u indicates this condition. the pin function is mode dependent. table 6-1. input/output ports port input pins output pins bidirectional pins shared functions port a 3 3 2 timer port d ?? 6 serial communications interface (sci) and serial peripheral interface (spi) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical summary mc68hc11ed0 ? rev. 1.0 parallel input/output (i/o) ports parallel input/output (i/o) ports 6.3 port a data register refer to figure 6-1 for a description of the port a data register (porta). to enable pa3 as fourth input capture, set i4/o5 bit in the pulse accumulator control register (pactl). otherwise, pa3 is configured as a fifth output compare out of reset, with bit i4/o5 being cleared. if the ddra3 bit in pactl is set (configuring pa3 as an output), and ic4 is enabled, writes to pa3 cause edges on the pin to result in input captures. writing to i4/o5 has no effect when the i4/o5 register is acting as ic4. pa7 drives the pulse accumulator input but also can be configured for general-purpose i/o or output compare. ddra7 bit in pactl configures pa7 for either input or output. note: even when pa7 is configured as an output, the pin still drives the pulse accumulator input. address: $0000 bit 7654321bit 0 read: pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 write: reset:u0 0 0uuuu alternate function: and/or: pai oc1 oc2 oc1 oc3 oc1 oc4 oc1 ic4/oc5 oc1 ic1 ? ic2 ? ic3 ? u = undefined figure 6-1. port a data register (porta) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . parallel input/output (i/o) ports pulse accumulator control register mc68hc11ed0 ? rev. 1.0 technical summary parallel input/output (i/o) ports 6.4 pulse accumulator control register refer to figure 6-2 for a description of the pulse accumulator control register (pactl). ddra7 ? data direction for port a bit 7 0 = input 1 = output paen ? pulse accumulator system enable bit refer to 9.4 pulse accumulator . pamod ? pulse accumulator mode bit refer to 9.4 pulse accumulator . pedge ? pulse accumulator edge control bit refer to 9.4 pulse accumulator . ddra3 ? data direction for port a bit 3 this bit is overridden if an output compare function is configured to control the pa3 pin. 0 = input 1 = output i4/o5 ? input capture 4/output compare 5 bit refer to section 9. timing system . rtr[1:0] ? real-time interrupt (rti) rate select bits refer to 9.4 pulse accumulator . address: $0026 bit 7654321bit 0 read: ddra7 paen pamod pedge ddra3 i4/o5 rtr1 rtr0 write: reset:00000000 figure 6-2. pulse accumulator control register (pactl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical summary mc68hc11ed0 ? rev. 1.0 parallel input/output (i/o) ports parallel input/output (i/o) ports 6.5 port d data register refer to figure 6-3 for a description of the port d data register (portd). address: $0008 bit 7654321bit 0 read: pd5 pd4 pd3 pd2 pd1 pd0 write: reset:0 0uuuuuu alternate function: ?? ss sck mosi miso txd rxd = unimplemented u = undefined figure 6-3. port d data register (portd) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . parallel input/output (i/o) ports port d data direction register mc68hc11ed0 ? rev. 1.0 technical summary parallel input/output (i/o) ports 6.6 port d data direction register refer to figure 6-4 for a description of the port d data direction register (ddrd) bits [7:6] ? unimplemented always read 0 ddd[5:0] ? port d data direction bits 0 = input 1 = output note: when the serial peripheral interface (spi) system is in slave mode, ddd5 has no meaning or effect. when the spi system is in master mode, ddd5 determines whether bit 5 of portd is an error detect input (ddd5 = 0) or a general-purpose output (ddd5 = 1). if the spi system is enabled and expects any of bits [4:2] to be an input, that bit will be an input regardless of the state of the associated ddr bit. if any of bits [4:2] are expected to be outputs, that bit will be an output only if the associated ddr bit is set. address: $0009 bit 7654321bit 0 read: ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 write: reset:00000000 = unimplemented figure 6-4. port d data direction register (ddrd) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical summary mc68hc11ed0 ? rev. 1.0 parallel input/output (i/o) ports parallel input/output (i/o) ports f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc11ed0 ? rev. 1.0 te c h n i c a l s u m m a r y serial communications interface (sci) technical data ? mc68hc11ed0 section 7. serial communications interface (sci) 7.1 contents 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 7.3 sci registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 7.3.1 baud rate register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.3.2 serial communications control register 1 . . . . . . . . . . . . . 77 7.3.3 serial communications control register 2 . . . . . . . . . . . . . 78 7.3.4 serial communication status register. . . . . . . . . . . . . . . . . 79 7.3.5 serial communications data register . . . . . . . . . . . . . . . . . 80 7.2 introduction the serial communications interface (sci) is a universal asynchronous receiver transmitter (uart), one of two independent serial input/output (i/o) subsystems in the mc68hc11ed0. it has a standard non-return to zero (nrz) format (one start bit, eight or nine data bits, and one stop bit) and several baud rates available. the sci transmitter and receiver are independent, but use the same data format and bit rate. refer to figure 7-1 and figure 7-2 . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical summary mc68hc11ed0 ? rev. 1.0 serial communications interface (sci) serial communications interface (sci) figure 7-1. sci transmitter block diagram fe nf or idle rdrf tc tdre sbk rwu re te ilie rie tcie tie transmitter control logic tcie tc tie tdre sci rx requests sci interrupt request internal data bus pin buffer and control h(8)76543210l 10 (11) - bit tx shift register ddd1 pd1 txd transfer tx buffer shift enable jam enable preamble ? jam 1s break ? jam 0s wri te only force pin direction (out) size 8/9 wake m t8 r8 transmitter baud rate clock 8 8 8 sccr1 sci control 1 scdr tx buffer scsr interrupt status sccr2 sci control 2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface (sci) introduction mc68hc11ed0 ? rev. 1.0 technical summary serial communications interface (sci) figure 7-2. sci receiver block diagram fe nf or idle rdrf tc tdre scsr sci status 1 sbk rwu re te ilie rie tcie tie sccr2 sci control 2 wake m t8 r8 wakeup logic rie or ilie idle sci tx requests sci interrupt request internal data bus pin buffer and control ddd0 pd0 rxd scdr rx buffer stop (8)76543210 10 (11) - bit rx shift register read only sccr1 sci control 1 rie rdrf start msb all 1s data recovery 16 rwu re m disable driver receiver baud rate clock 8 8 8 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical summary mc68hc11ed0 ? rev. 1.0 serial communications interface (sci) serial communications interface (sci) 7.3 sci registers this subsection describes the sci registers. 7.3.1 baud rate register tclr ? clear baud rate counter bit tclr can be set only in test modes. 1 = clear baud rate counter chain for testing purposes 0 = normal sci operation scp[1:0] ? sci baud rate prescaler select bits refer to table 7-1 for the prescaler rates. the shaded boxes contain the prescaler rates used in the table 7-2 . address: $002b bit 7654321bit 0 read: tclr scp1 scp0 rckb scr2 scr1 scr0 write: reset:00000uuu = unimplemented u = unaffected figure 7-3. baud rate register (baud) table 7-1. prescaler rates scp[1:0] divide e clock by crystal frequency in mhz 4.0 mhz (baud) 8.0 mhz (baud) 12.0 mhz (baud) 0 0 1 62.50 k 125.0 k 187.5 k 0 1 3 20.83 k 41.67 k 62.5 k 1 0 4 15.625 k 31.25 k 46.88 k 1 1 13 4800 9600 14.4 k f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface (sci) sci registers mc68hc11ed0 ? rev. 1.0 technical summary serial communications interface (sci) rckb ? sci baud rate clock check bit rckb can be set only in test modes. 1 = exclusive-or of the rt clock driven out txd pin for testing purposes 0 = normal sci operation scr[2:0] ? sci baud rate select bits these bits select receiver and transmitter bit rates based on output from the baud rate prescaler stage. refer to table 7-2 and figure 7-4 . table 7-2. baud rates scr[2:0] divide prescaler by baud rate (prescaler output from table 7-1 ) 4800 9600 14.4 k 0 0 0 1 4800 9600 14.4 k 0 0 1 2 2400 4800 7200 0 1 0 4 1200 2400 3600 0 1 1 8 600 1200 1800 1 0 0 16 300 600 1200 1 0 1 32 150 300 450 1 1 0 64 75 150 225 1 1 1 128 37.5 75 112.5 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical summary mc68hc11ed0 ? rev. 1.0 serial communications interface (sci) serial communications interface (sci) figure 7-4. sci baud rate generator clock diagram 0:0:0 2 0:0:1 2 0:1:0 2 0:1:1 2 1:0:0 2 1:0:1 2 1:1:0 2 sci transmit baud rate (1x) sci receive baud rate (16x) 16 1:1:1 scr[2:0] 3 0:0 4 13 0:1 1:0 1:1 oscillator and clock generator ( 4) scp[1:0] internal bus clock (ph2) e as extal xtal f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface (sci) sci registers mc68hc11ed0 ? rev. 1.0 technical summary serial communications interface (sci) 7.3.2 serial communications control register 1 r8 ? receive data bit 8 if m bit is set, r8 stores the ninth bit in the receive data character. t8 ? transmit data bit 8 if m bit is set, t8 stores the ninth bit in the transmit data character. bit 5 ? unimplemented always reads 0 m ? mode bit (select character format) 1 = start bit, 8 data bits, 1 stop bit 1 = start bit, 9 data bits, 1 stop bit wake ? wakeup by address mark/idle bit 0 = wakeup by idle line recognition 1 = wakeup by address mark (most significant data bit set) bits [2:0] ? unimplemented always read 0 address: $002c bit 7654321bit 0 read: r8 t8 mwake write: reset:00000000 = unimplemented figure 7-5. serial communications control register 1 (sccr1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical summary mc68hc11ed0 ? rev. 1.0 serial communications interface (sci) serial communications interface (sci) 7.3.3 serial communications control register 2 tie ? transmit interrupt enable bit 0 = tdre interrupts disabled 1 = sci interrupt requested when tdre status flag is set tcie ? transmit complete interrupt enable bit 0 = tc interrupts disabled 1 = sci interrupt requested when tc status flag is set rie ? receiver interrupt enable bit 0 = rdrf and or interrupts disabled 1 = sci interrupt requested when rdrf flag or the or status flag is set ilie ? idle-line interrupt enable bit 0 = idle interrupts disabled 1 = sci interrupt requested when idle status flag is set te ? transmitter enable bit 0 = transmitter disabled 1 = transmitter enabled re ? receiver enable bit 0 = receiver disabled 1 = receiver enabled rwu ? receiver wakeup control bit 0 = normal sci receiver 1 = wakeup enabled and receiver interrupts inhibited sbk ? send break bit 0 = break generator off 1 = break codes generated as long as sbk = 1 address: $002d bit 7654321bit 0 read: tie tcie rie ilie te re rwu sbk write: reset:00000000 figure 7-6. serial communications control register 2 (sccr2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial communications interface (sci) sci registers mc68hc11ed0 ? rev. 1.0 technical summary serial communications interface (sci) 7.3.4 serial communication status register tdre ? transmit data register empty flag this flag is set when scdr is empty. clear the tdre flag by reading scsr and then writing to scdr. 0 = scdr busy 0 = scdr empty tc ? transmit complete flag this flag is set when the transmitter is idle (no data, preamble, or break transmission in progress). clear the tc flag by reading scsr and then writing to scdr. 0 = transmitter busy 1 = transmitter idle rdrf ? receive data register full flag this flag is set if a received character is ready to be read from scdr. clear the rdrf flag by reading scsr and then reading scdr. 0 = scdr empty 1 = scdr full idle ? idle line detected flag this flag is set if the rxd line is idle. once cleared, idle is not set again until the rxd line has been active and becomes idle again. the idle flag is inhibited when rwu = 1. clear idle by reading scsr and then reading scdr. 0 = rxd line active 1 = rxd line idle address: $002e bit 7654321bit 0 read: tdre tc rdrf idle or nf fe write: reset:11000000 = unimplemented figure 7-7. serial communications status register (scsr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical summary mc68hc11ed0 ? rev. 1.0 serial communications interface (sci) serial communications interface (sci) or ? overrun error flag or is set if a new character is received before a previously received character is read from scdr. clear the or flag by reading scsr and then reading scdr. 0 = no overrun 1 = overrun detected nf ? noise error flag nf is set if majority sample logic detects anything other than a unanimous decision. clear nf by reading scsr and then reading scdr. 0 = unanimous decision 1 = noise detected fe ? framing error flag fe is set when a 0 is detected where a stop bit was expected. clear the fe flag by reading scsr and then reading scdr. 0 = stop bit detected 1 = zero detected bit 0 ? unimplemented always reads 0 7.3.5 serial communications data register note: sci receive and transmit data are double buffered. reads of scdr access the receive data buffer and writes access the transmit data buffer. address: $002f bit 7654321bit 0 read: r7/t7 r6/t6 r5/t5 r4/t4 r3/t3 r2/t2 r1/t1 r0/t0 write: reset: unaffected by reset figure 7-8. serial communications data register (scdr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc11ed0 ? rev. 1.0 te c h n i c a l s u m m a r y serial peripheral interface (spi) technical data ? mc68hc11ed0 section 8. serial peripheral interface (spi) 8.1 contents 8 . 2 i n trod u ctio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1 8 . 3 sp i registe r s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 8 . 3.1 s er i a l p e r i phe r al c ont r o l r eg i st e r . . . . . . . . . . . . . . . . . . . . 8 3 8 . 3.2 s er i a l p e r i phe r al s tatus r e g i ster . . . . . . . . . . . . . . . . . . . . . 8 5 8 . 3.3 s eri a l p e r i phe r al data i/o regist e r . . . . . . . . . . . . . . . . . . . 8 6 8.2 introduction the serial peripheral interface (spi) allows the microcontroller unit (mcu) to communicate synchronously with peripheral devices and other microprocessors. when configured as a master, data transfer rates can be as high as one-half the e clock rate (1.5 mbits per second for a 3-mhz bus frequency). when configured as a slave, data transfers can be as fast as the e-clock rate (3 mbits per second for a 3-mhz bus frequency). when the spi is enabled, all pins that are defined by the configuration as inputs are inputs regardless of the state of the ddr bits of those pins. all pins that are defined as outputs will be outputs only if the ddr bits for those pins are set to 1. any spi output whose corresponding ddr bit is cleared to 0 can be used as a general-purpose input. if the spi system is in master mode and ddrd bit 5 is set to 1, the port d bit 5 pin becomes a general-purpose output instead of the ss input to the spi system. the modf mode error flag function for which ss was used becomes disabled to avoid interference between the general-purpose output function and the spi system. ref e r to f i g u r e 8 - 1 , w h i c h s h o w s the sp i b l ock d i agr a m . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical summary mc68hc11ed0 ? rev. 1.0 serial peripheral interface (spi) serial peripheral interface (spi) figure 8-1. spi block diagram 8/16-bit shift register read data buffer msb lsb miso pd2 mosi pd3 sck pd4 ss pd5 divider 2 4 16 3 2 internal mcu clock select s m m s s m pin control logic clock logic clock spie spe dwom mstr cpol cpha spr1 spr0 spi control register mstr spe dwom spr0 spr1 mstr spe spi control spif wcol mode spi status register spi interrupt request internal data bus 8 8 8 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface (spi) spi registers mc68hc11ed0 ? rev. 1.0 technical summary serial peripheral interface (spi) 8.3 spi registers this subsection describes the spi registers. 8.3.1 serial peripheral control register spie ? serial peripheral interrupt enable bit 0 = spi interrupts disabled 1 = spi interrupts enabled spe ? serial peripheral system enable bit 0 = spi off 1 = spi on dwom ? port d wired-or mode option bit for port d pins pd[5:2] 0 = normal cmos outputs 1 = open-drain outputs mstr ? master mode select bit 0 = slave mode 1 = master mode c p ol a n d c p h a ? cl o ck p o l a r i ty b i t and c l o ck p h ase b i t ref e r to f i g u r e 8 - 3 . address: $0028 bit 7654321bit 0 read: spie spe dwom mstr cpol cpha spr1 spr0 write: reset:000001uu u = unaffected figure 8-2. serial peripheral control register (spcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical summary mc68hc11ed0 ? rev. 1.0 serial peripheral interface (spi) serial peripheral interface (spi) figure 8-3. spi transfer format spr[1:0] ? spi clock rate select bits ref e r to ta b l e 8 - 1 . 2345678 1 sck (cpol = 1) sck (cpol = 0) sck cycle # ss (to slave) 654321 lsb msb msb654321lsb sample input data out (cpha = 0) sample input data out (cpha = 1) for reference table 8-1. spi clock rate selects spr[1:0] divide e clock by frequency at e = 1 mhz frequency at e = 2 mhz frequency at e = 3 mhz 0 0 2 500 khz 1.0 mhz 1.5 mhz 0 1 4 250 khz 500 khz 750 khz 1 0 16 125 khz 125 khz 375 khz 1 1 32 62.5 khz 62.5 khz 187.5 khz f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . serial peripheral interface (spi) spi registers mc68hc11ed0 ? rev. 1.0 technical summary serial peripheral interface (spi) 8.3.2 serial peripheral status register spif ? spi transfer complete flag this flag is set when an spi transfer is complete (after eight sck cycles in a data transfer). clear this flag by reading spsr, then access spdr. 0 = no spi transfer complete or spi transfer still in progress 1 = spi transfer complete wcol ? write collision error flag this flag is set if the mcu tries to write data into spdr while an spi data transfer is in progress. clear this flag by reading spsr, then access spdr. 0 = no write collision error 1 = spdr written while spi transfer in progress bit 5 ? unimplemented always reads 0 modf ? mode fault bit (mode fault terminates spi operation) set when ss is pulled low while mstr = 1. cleared by spsr read followed by spcr write. 0 = no mode fault error 1 = ss pulled low in master mode bits [3:0] ? unimplemented always read 0 address: $0029 bit 7654321bit 0 read: spif wcol modf write: reset:00000000 = unimplemented figure 8-4. serial peripheral status register (spsr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical summary mc68hc11ed0 ? rev. 1.0 serial peripheral interface (spi) serial peripheral interface (spi) 8.3.3 serial peripheral data i/o register spi is double buffered in and single buffered out. address: $002a bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: indeterminate after reset figure 8-5. serial peripheral data i/o register (spdr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc11ed0 ? rev. 1.0 te c h n i c a l s u m m a r y timing system technical data ? mc68hc11ed0 section 9. timing system 9.1 contents 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 9.3 timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 9.3.1 timer compare force register . . . . . . . . . . . . . . . . . . . . . . 91 9.3.2 output compare 1 mask register . . . . . . . . . . . . . . . . . . . . 92 9.3.3 output compare 1 data register. . . . . . . . . . . . . . . . . . . . . 92 9.3.4 timer count register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 9.3.5 timer input capture registers . . . . . . . . . . . . . . . . . . . . . . .94 9.3.6 timer output compare registers . . . . . . . . . . . . . . . . . . . . 95 9.3.7 timer input capture 4/output compare 5 register . . . . . . .96 9.3.8 timer control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 9.3.9 timer control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 9.3.10 timer interrupt mask 1 register. . . . . . . . . . . . . . . . . . . . . . 99 9.3.11 timer interrupt flag 1 register . . . . . . . . . . . . . . . . . . . . .100 9.3.12 timer interrupt mask 2 register. . . . . . . . . . . . . . . . . . . . .100 9.3.13 timer interrupt flag register 2 . . . . . . . . . . . . . . . . . . . . .102 9.4 pulse accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 9.4.1 pulse accumulator control register . . . . . . . . . . . . . . . . . 104 9.4.2 pulse accumulator counter register . . . . . . . . . . . . . . . . .106 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical summary mc68hc11ed0 ? rev. 1.0 timing system timing system 9.2 introduction the timing system is based on a free-running 16-bit counter with a four-stage programmable prescaler. a timer overflow function allows software to extend the system ? s timing capability beyond the counter ? s 16-bit range. the timer has: three channels for input capture four channels for output compare one channel that can be configured as a fourth input capture or a fifth output compare in addition, the timing system includes pulse accumulator and real-time interrupt (rti) functions, as well as a clock monitor function, which can be used to detect clock failures that are not detected by the computer operating properly (cop. refer to 9.4 pulse accumulator for further information about these functions. table 9-1 provides a summary of the crystal-related frequencies and periods. a block diagram of the timer system is shown in figure 9-1 . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timing system introduction mc68hc11ed0 ? rev. 1.0 technical summary timing system table 9-1. timer summary common system frequencies definition control bits 4.0 mhz 8.0 mhz 12.0 mhz xtal 1.0 mhz 2.0 mhz 3.0 mhz e pr[1:0] main timer count rates (period length) 0 0 1 count ? overflow ? 1000 ns 65.536 ms 500 ns 32.768 ms 333 ns 21.845 ms 1 e 2 16 e 0 1 1 count ? overflow ? 4.0 s 262.14 ms 2.0 s 131.07 ms 1.333 s 87.381 ms 4 e 2 18 e 1 0 1 count ? overflow ? 8.0 s 524.28 ms 4.0 s 262.14 ms 2.667 s 174.76 ms 8 e 2 19 e 1 1 1 count ? overflow ? 16.0 s 1.049 s 8.0 s 524.29 ms 5.333 s 349.52 ms 16 e 2 20 e rtr[1:0] periodic (rti) interrupt rates (period length) 0 0 0 1 1 0 1 1 8.192 ms 16.384 ms 32.768 ms 65.536 ms 4.096 ms 8.192 ms 16.384 ms 32.768 ms 2.731 ms 5.461 ms 10. 923 ms 21.845 ms 2 13 e 2 14 e 2 15 e 2 16 e cr[1:0] cop watchdog timeout rates (period length) 0 0 0 1 1 0 1 1 32.768 ms 131.072 ms 524.288 ms 2.098 s 16.384 ms 65.536 ms 262.14 ms 1.049 s 10.923 ms 43.691 ms 174.76 ms 699.05 ms 2 15 e 2 17 e 2 19 e 2 21 e timeout tolerance ( ? 0 ms / +...) 32.8 ms 16.4 ms 10.9 ms 2 15 e f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical summary mc68hc11ed0 ? rev. 1.0 timing system timing system figure 9-1. timer block diagram capture compare block mcu e clk 16-bit latch clk pa0/ic3 4 3 5 6 7 8 2 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 port a pin control oc1i oc2i oc3i oc4i i4/o5i ic1i ic2i ic3i tflg 1 status flags foc1 foc2 foc3 foc4 foc5 oc1f oc2f oc3f oc4f i4/o5f ic1f ic2f ic3f pa1/ic2 pa2/ic1 pa3/oc5/ ic4/oc1 pa4/oc4/ oc1 pa5/oc3/ oc1 pa6/oc2/ oc1 pa7/oc1/ pai i4/o5 16-bit comparator = toc1 (hi) toc1 (lo) 16-bit comparator = toc2 (hi) toc2 (lo) 16-bit comparator = toc3 (hi) toc3 (lo) 16-bit comparator = toc4 (hi) toc4 (lo) 16-bit latch tic1 (hi) tic1 (lo) clk 16-bit latch tic2 (hi) tic2 (lo) clk 16-bit latch tic3 (hi) tic3 (lo) clk 16-bit comparator = ti4/o5 (hi) ti4/o5 (lo) 16-bit free-running counter tcnt (hi) tcnt (lo) 9 toi tof interrupt requests (further qualified by i bit in ccr) taps for rti, cop watchdog, and pulse accumulator prescaler divide by 1, 4, 8, or 16 pr1 pr0 16-bit timer bus oc5 ic4 to pulse accumulator tmsk 1 interrupt enables cforc force output compare pin functions f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timing system timer registers mc68hc11ed0 ? rev. 1.0 technical summary timing system 9.3 timer registers this subsection provides a description of the registers associated with the timer system. 9.3.1 timer compare force register foc[5:1] ? force output compare bits write 1s to force compare(s) 0 = not affected 1 = output x action occurs bits [2:0] ? unimplemented always read 0 address: $000b bit 7654321bit 0 read: foc1 foc2 foc3 foc4 foc5 write: reset:00000000 = unimplemented figure 9-2. timer compare force register (cforc) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical summary mc68hc11ed0 ? rev. 1.0 timing system timing system 9.3.2 output compare 1 mask register oc1m[7:3] ? output compare 1 mask bits set bit(s) to enable oc1 to control corresponding pin(s) of port a bits [2:0] ? unimplemented always read as 0 9.3.3 output compare 1 data register oc1d[7:3] ? output compare 1 data bits if oc1mx is set, data in oc1dx is output to port a bit x on successful oc1 compares. bits [2:0] ? unimplemented always read 0 address: $000c bit 7654321bit 0 read: oc1m7 oc1m6 oc1m5 oc1m4 oc1m3 write: reset:00000000 = unimplemented figure 9-3. output compare 1 mask register (oc1m) address: $000d bit 7654321bit 0 read: oc1d7 oc1d6 oc1d5 oc1d4 oc1d3 write: reset:00000000 = unimplemented figure 9-4. output compare 1 data register (oc1d) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timing system timer registers mc68hc11ed0 ? rev. 1.0 technical summary timing system 9.3.4 timer count register the timer count register (tcnt) is read only in normal modes. address: $000e ? high bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 address: $000f ? low read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 = unimplemented figure 9-5. timer count register (tcnt) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical summary mc68hc11ed0 ? rev. 1.0 timing system timing system 9.3.5 timer input capture registers address: $0010 ? high bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: unaffected by reset address: $0011 ? low read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: unaffected by reset figure 9-6. timer input capture register 1 (tic1) address: $0012 ? high bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: unaffected by reset address: $0013 ? low read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: unaffected by reset figure 9-7. timer input capture register 2 (tic2) address: $0014 ? high bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: unaffected by reset address: $0015 ? low read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: unaffected by reset figure 9-8. timer input capture register 3 (tic3) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timing system timer registers mc68hc11ed0 ? rev. 1.0 technical summary timing system 9.3.6 timer output compare registers address: $0016 ? high bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:11111111 address: $0017 ? low read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:11111111 figure 9-9. timer output compare register 1 (toc1) address: $0018 ? high bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:11111111 address: $0019 ? low read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:11111111 figure 9-10. timer output compare register 2 (toc2) address: $001a ? high bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:11111111 address: $001b ? low read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:11111111 figure 9-11. timer output compare register 3 (toc3) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical summary mc68hc11ed0 ? rev. 1.0 timing system timing system 9.3.7 timer input capture 4/output compare 5 register this is a shared register and is either input capture 4 or output compare 5 depending on the state of bit i4/o5 in pactl. writes to ti4/o5 have no effect when this register is configured as input capture 4. address: $001c ? high bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:11111111 address: $001d ? low read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:11111111 figure 9-12. timer output compare register 4 (toc4) address: $001e ? high bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:11111111 address: $001f ? low read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:11111111 figure 9-13. timer input capture4/output compare 5 register (ti4/o5) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timing system timer registers mc68hc11ed0 ? rev. 1.0 technical summary timing system 9.3.8 timer control register 1 om[5:2] ? output mode ol[5:2] ? output level see table 9-2 . address: $0020 bit 7654321bit 0 read: om2 ol2 om3 ol3 om4 ol4 om5 ol5 write: reset:00000000 figure 9-14. timer control register 1 (tctl1) table 9-2. timer output compare actions omx olx action taken on successful compare 0 0 timer disconnected from output pin logic 0 1 toggle ocx output line 1 0 clear ocx output line to 0 1 1 set ocx output line to 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical summary mc68hc11ed0 ? rev. 1.0 timing system timing system 9.3.9 timer control register 2 address: $0021 bit 7654321bit 0 read: edg4b edg4a edg1b edg1a edg2b edg2a edg3b edg3a write: reset:00000000 figure 9-15. timer control register 2 (tctl2) table 9-3. timer control configuration edgxb edgxa configuration 0 0 capture disabled 0 1 capture on rising edges only 1 0 capture on falling edges only 1 1 capture on any edge f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timing system timer registers mc68hc11ed0 ? rev. 1.0 technical summary timing system 9.3.10 timer interrupt mask 1 register oc1i ? oc4i ? output compare interrupt enable bits if the ocxf flag bit is set while the ocxi enable bit is set, a hardware interrupt sequence is requested. i4/oc5i ? input capture 4 or output compare 5 interrupt enable bit when i4/o5 in pactl is 1, i4/o5i is the input capture 4 interrupt bit. when i4/o5 in pactl is 0, i4/o5i is the output compare 5 interrupt control bit. ic1i ? ic3i ? input capture interrupt enable bits if the icxf flag bit is set while the icxi enable bit is set, a hardware interrupt sequence is requested. note: control bits in tmsk1 correspond bit for bit with flag bits in tflg1. ones in tmsk1 enable the corresponding interrupt sources. address: $0022 bit 7654321bit 0 read: oc1i oc2i oc3i oc4i i4/o5i ic1i ic2i ic3i write: reset:00000000 figure 9-16. timer interrupt mask 1 register (tmsk1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical summary mc68hc11ed0 ? rev. 1.0 timing system timing system 9.3.11 timer interrupt flag 1 register clear flags by writing a 1 to the corresponding bit position(s). oc1f ? oc4f ? output compare x flags set each time the counter matches output compare x value i4/o5f ? input capture 4/output compare 5 flag set by ic4 or oc5, depending on which function was enabled by i4/o5 of pactl ic1f ? ic3f ? input capture x flag set each time a selected active edge is detected on the icx input line 9.3.12 timer interrupt mask 2 register toi ? timer overflow interrupt enable bit 0 = timer overflow interrupt disabled 1 = timer overflow interrupt enabled address: $0023 bit 7654321bit 0 read: oc1f oc2f oc3f oc4f i4/o5f ic1f ic2f ic3f write: reset:00000000 figure 9-17. timer interrupt flag 1 register (tflg1) address: $0024 bit 7654321bit 0 read: toi rtii paovi paii pr1 pr0 write: reset:00000000 = unimplemented figure 9-18. timer interrupt mask 2 register (tmsk2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timing system timer registers mc68hc11ed0 ? rev. 1.0 technical summary timing system rtii ? real-time interrupt enable bit 0 = rtif interrupts disabled 1 = interrupt requested when rtif is set to 1 paovi ? pulse accumulator overflow interrupt enable bit refer to 9.4 pulse accumulator . paii ? pulse accumulator interrupt enable bit refer to 9.4 pulse accumulator . bits [3:2] ? unimplemented always read as 0 pr[1:0] ? timer prescaler select bits in normal modes, pr1 and pr0 can be written only once, and the writes must occur within 64 cycles after reset. refer to table 9-1 and table 9-4 for specific timing values. note: control bits [7:4] in tmsk2 correspond bit for bit with flag bits [7:4] in tflg2. logic 1s in tmsk2 enable the corresponding interrupt sources. table 9-4. timer prescale pr[1:0] prescaler 0 0 1 0 1 4 1 0 8 1 1 16 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical summary mc68hc11ed0 ? rev. 1.0 timing system timing system 9.3.13 timer interrupt flag register 2 clear flags by writing a 1 to the corresponding bit position(s). tof ? timer overflow interrupt flag set when tcnt changes from $ffff to $0000 rtif ? real-time (periodic) interrupt flag set periodically. refer to the description of bits rtr[1:0] in figure 9-21 . paovf ? pulse accumulator overflow flag refer to 9.4 pulse accumulator . paif ? pulse accumulator input edge flag refer to 9.4 pulse accumulator . bits [3:0] ? unimplemented always read 0 address: $0025 bit 7654321bit 0 read: tof rtif paovf paif write: reset:00000000 = unimplemented figure 9-19. timer interrupt flag 2 register (tflg2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timing system pulse accumulator mc68hc11ed0 ? rev. 1.0 technical summary timing system 9.4 pulse accumulator the mc68hc11ed0 has an 8-bit counter that can be configured as a simple event counter or for gated time accumulation. the counter can be read or written at any time. the port a bit 7 i/o pin can be configured to act as a clock in event counting mode, or as a gate signal to enable a free-running clock (e divided by 64) to the 8-bit counter in gated time accumulation mode. refer to figure 9-1 and table 9-5 . figure 9-20. pulse accumulator system block diagram pedge pamod paen pactl control internal data bus pacnt 8-bit counter pa7/ pai/ oc1 interrupt requests paif paovf tflg2 interrupt status paovi paii paovf paovi paif paii tmsk2 int enables 1 2 overflow enable disable flag setting clock pai edge paen paen 2 : 1 mux output buffer input buffer and edge detector from main timer oc1 data bus mcu pin e 64 clock from main timer from ddra7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical summary mc68hc11ed0 ? rev. 1.0 timing system timing system pulse accumulator control bits are also located within two timer registers, tmsk2 and tflg2, as described in 9.4.1 pulse accumulator control register . 9.4.1 pulse accumulator control register ddra7 ? data direction for port a bit 7 refer to section 6. parallel input/output (i/o) ports . paen ? pulse accumulator system enable bit 0 = pulse accumulator disabled 1 = pulse accumulator enabled pamod ? pulse accumulator mode bit 0 = event counter 1 = gated time accumulation table 9-5. pulse accumulator timing common xtal frequencies 4.0 mhz 8.0 mhz 12.0 mhz cpu clock (e) 1.0 mhz 2.0 mhz 3.0 mhz cycle time (1 e) 1000 ns 500 ns 333 ns pulse accumulator (gated mode) 1 count (2 6 e) 64.0 s 32.0 s 21.330 s overflow 2 14 e) 16.384 ms 8.192 ms 5.491 ms address: $0026 bit 7654321bit 0 read: ddra7 paen pamod pedge ddra3 i4/o5 rtr1 rtr0 write: reset:00000000 figure 9-21. pulse accumulator control register (pactl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timing system pulse accumulator mc68hc11ed0 ? rev. 1.0 technical summary timing system pedge ? pulse accumulator edge control bit 0 = in event mode, falling edges increment counter. in gated accumulation mode, high level enables accumulator and falling edge sets paif. 1 = in event mode, rising edges increment counter. in gated accumulation mode, low level enables accumulator and rising edge sets paif. ddra3 ? data direction for port a bit 3 refer to section 6. parallel input/output (i/o) ports . i4/o5 ? input capture 4/output compare bit configure ti4/o5 for input capture or output compare 0 = oc5 enabled 1 = ic4 enabled rtr[1:0] ? rti interrupt rate select bits these two bits select the rate for periodic interrupts. refer to table 9-6 and table 9-7 . table 9-6. rti rates (period length) rtr[1:0] period length selected period length e = 1.0 mhz e = 2.0 mhz e = 3.0 mhz 0 0 2 13 e 8.19 ms 4.096 ms 2.731 ms 0 1 2 14 e 16.38 ms 8.192 ms 5.461 ms 1 0 2 15 e 32.77 ms 16.384 ms 10.923 ms 1 1 2 16 e 65.54 ms 32.768 ms 21.845 ms table 9-7. rti rates (frequency) rtr[1:0] rate selected frequency e = 1.0 mhz e = 2.0 mhz e = 3.0 mhz 0 0 e 2 13 122.070 hz 244.141 hz 366.211 hz 0 1 e 2 14 61.035 hz 122.070 hz 183.105 hz 1 0 e 2 15 30.518 hz 61.035 hz 91.553 hz 1 1 e 2 16 15.259 hz 30.518 hz 45.776 hz f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . technical summary mc68hc11ed0 ? rev. 1.0 timing system timing system 9.4.2 pulse accumulator counter register refer to figure 9-22 for a description of the pulse accumulator counter register (pacnt). address: $0027 bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: unaffected by reset figure 9-22. pulse accumulator counter register (pacnt) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . blank f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc 1 1ed0ts/d rev 1 m 68h11e series technical data f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . |
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